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Srinivasan, G.K. Multi-Level Inverter. Encyclopedia. Available online: https://encyclopedia.pub/entry/7623 (accessed on 15 June 2024).
Srinivasan GK. Multi-Level Inverter. Encyclopedia. Available at: https://encyclopedia.pub/entry/7623. Accessed June 15, 2024.
Srinivasan, Ganesh Kumar. "Multi-Level Inverter" Encyclopedia, https://encyclopedia.pub/entry/7623 (accessed June 15, 2024).
Srinivasan, G.K. (2021, February 27). Multi-Level Inverter. In Encyclopedia. https://encyclopedia.pub/entry/7623
Srinivasan, Ganesh Kumar. "Multi-Level Inverter." Encyclopedia. Web. 27 February, 2021.
Multi-Level Inverter
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Multilevel inverter had been paid a lot of attention from the academia and research community in recent times due to its role in high and medium power applications. 

cascaded unit 81-level induction motor ladder circuit multilevel inverter pulse generation

1. Introduction

Nowadays, multilevel inverters (MLI) play a major role in various power applications such as Electric Vehicle[1], Photovoltaic systems[2], Low-Power Loads[3], Grid integration system[4]. It is more attractive because of very low harmonic distortion, low number of drivers, absence of filters, low installation area, reduction in voltage stress and switching losses.

A generalized cascaded multilevel inverter is presented with nearest level modulation technique. The proposed converter is discussed with and without half bridge circuits[4]. A new multilevel inverter with one DC source is presented for low power applications. The proposed inverter generates the output voltage eight times higher than the input voltage[3]. In[4], various configurations of MLI’s were analyzed in terms of number of switching devices and modulation techniques. MLI are broadly classified into cascaded H Bridge, neutral clamped and flying capacitor topologies[5].

Recently, for hybrid systems cascade multilevel inverters are applied. Many topologies are there to create the staircase voltages with higher levels with low devices count[6]. A new MLI is designed to generate generate 27-level and fifty one level output voltages using constant voltage sources for resistive-inductive load[7]. An inverter is designed using trinary DC sources and thirteen switches to generate 53 output levels with minimum THD of 1.15% [8]. A new switched source MLI is proposed which operates under both symmetric and asymmetric mode. The proposed inverter is designed with six power switches and two voltage sources[9]. A new 81-level MLI is presented using two stage ladder circuits and the values of the dc sources are fixed by two different algorithms. The presented topology is tested with resistive and impedance load[10]. A cascaded MLI is presented to generate 9, 15, 27, 33 and 39 output voltage levels at the load. It is observed that increase in number of voltage levels reduces the presence of harmonic content in load voltage and current waveforms. The proposed inverter is simulated in Matlab/Simulink and analyzed the total harmonic distortion for resistive and resistive-inductive load[11]. Various configurations of symmetrical, asymmetrical and hybrid MLI’s were synthesized in terms of number of switches, capacitors, diodes utilized in the inverter circuit. As well, an analyzes is made in terms of THD generation and total standing voltages of all the configurations[12]. Few drawbacks such as: switch count, voltage imbalance and number of DC sources are there in all the topologies[13].

Multilevel inverter with minimum switch count is focused nowadays with higher voltage levels[14]. Higher voltage levels are attained using cascaded H bridge MLI with isolated DC voltage sources. The switch count reduction is based on the design of basic unit. MLI with three phase is proposed with reduced power switches and has attained nine output voltage levels. The proposed structure is analyzed for various pulse width modulation (PWM) techniques. Total harmonic distortion is examined for all the PWM techniques[15].

A new optimized structure of MLI is designed to create a rectangular type and circular type with a smaller number of switching components. A new switching technique is adopted and it is validated through simulation and experimental studies[16]. A three phase cascade H bridge (CHB) inverter is proposed with discontinuous pulse width modulation which reduces switching losses and thus increases the lifetime of the switches. MLI also adopted with rotation scheme for even distribution of power in the switches[17]. A trinary CHB MLI is proposed for solar power system with equal number of voltage levels.

For the control of active power and grid interaction, a modified second order integral control is applied[18]. The space vector pulse width modulation scheme is being applied to the MLI for common mode voltage reduction[19]. Two new MLI structures are designed and interfaced with PV system. Both the MLI structures consists of equal number of power switches and generates 9-level output[20].

2. Issues in MLI with Low Device Count

In MLI, there are issues such as: Voltage unbalancing, gate pulse generation and circuit complexity. The major issues in various MLI topologies are discussed in Table 3. Some of the challenges are discussed below. In[20] additional power stage is used, a transformer along with the inverter which increases the cost. Reactive power capability is absent in the structure proposed in[20]. The design structure presented in[21][22] requires a greater number of components for constructing higher number of levels. The design topology in[23] uses bidirectional switches which increases the cost and size of the inverter. The inverter topology in[24][25] utilizes more circuit components to generate higher output voltage levels. The reduction of harmonic content in the output load waveform is challenging and it is presented in[26]. Inverter proposed in[27] has higher total standing voltages. The presented topology in[28][29] requires more circuits to achieve more output levels. A complex control is necessary in-order to design a bi-direction MLI[30]. Voltage balance in the capacitor is challenging in the switched capacitor MLI with reduced switch count[31]. Balancing the voltage in DC link needs high attention[32]. The configuration presented in [33] utilizes more switches to generate higher number of voltage levels. In[34], the basic structure of proposed system requires two bidirectional switches and it is used to generate 17-levels in the output via asymmetrical configuration. In order to increase the output levels by cascading the SLMLI unit or increasing the ladder structure that is ‘m’, the total voltage appeared across the switches Sx and Sy is becoming high and it increases the rating of the devices. Furthermore, the switching frequency is high to generate desired output levels which increases switching losses.

Table 3. Issues in MLIRS.

In[35], various topologies of MLI were designed using higher number of voltage sources with less number of switches to achieve more output voltage levels and the issues found in the configurations are listed in Table 2. In[36][37], a symmetric multilevel inverter is designed and found failure in the implementation of medium and high voltage applications. In[38][39], a multilevel inverter is designed using asymmetrical voltage sources to generate more output voltages levels with increase in the number of switches. A hybrid MLI designed with complex control technique and it is presented in[40].

In[41], the proposed system is used to generate 9-levels in the output with four dc sources, eight switches and four diodes. While extending the output voltage levels, more units are added and thus conduction and switching losses are more. In addition to increase in switching loss, stress across the switch is increasing.

Circuit proposed in[42] consists of single source and double sources configuration to build multi levels in the output by connecting the sources in series and parallel. For this configuration there is a possibility of short circuit of DC sources while turning on the sources and voltage stresses between the switches is high. A Cascaded switched diode MLI is designed utilizing more number of diodes[43].

In[44], proposed cascaded switched diode structure consists of two stages. First stage contains dc sources, switch and diode. The second stage is an H-bridge inverter, in order to increase the multilevel in the output, number of units in the first stage is increased and thus large number of switches and diodes are required.

Conventional diode clamped and capacitor clamped multilevel inverters[45] are modified by adding single phase full bridge inverter. This proposed system reduces the number of switches but the requirement of diodes and capacitors are increased compared to the conventional inverters.

Significant factors of inverter design using Asymmetric voltage sources presented in[46] is identified and tabulated in Table 2. As well, few of the challenges in the reduced switch MLI[47], Asymmetric MLI[48] and modularized MLI [49] were identified and listed in Table 2.

In[50], 9-levels of output voltage are generated using 12 numbers of switches and 4 number of dc sources. In order to construct each level of output waveform, six switches are required to be turned on at an instant and thus switching losses are increasing. A 9-level symmetric and 31 level asymmetric inverter were simulated using a smaller number of voltage sources[51]. Using large number of switches, a symmetric MLI topology is designed and experimented in [52]. Also various topologies of MLI were designed using optimal number of switches[53][54][55][56][57].

References

  1. Roemer, F.; Ahmad, M.; Chang, F.; Lienkamp, M. Optimization of a cascaded h-bridge inverter for electric vehicle applications including cost consideration. Energies 2019, 12, 4272.
  2. Karthikeyan, D.; Vijayakumar, K.; Jagabar Sathik, M. Generalized cascaded symmetric and level doubling multilevel converter topology with reduced THD for photovoltaic applications. Electronics 2019, 8, 161.
  3. Samadaei, E.; Salehi, A.; Iranian, M.; Pouresmaeil, E. Single DC source multilevel inverter with changeable gains and levels for low-power loads. Electronics 2020, 9, 937.
  4. Sunddararaj, S.P.; Srinivasarangan Rangarajan, S.; Subashini, N. An extensive review of multilevel inverters based on their multifaceted structural configuration, triggering methods and applications. Electronics 2020, 9, 433.
  5. Vijayaraja, L.; Kumar, S.G.; Rivera, M. A review on multilevel inverter with reduced switch count. In Proceedings of the 2016 IEEE International Conference on Automatica (ICA-ACCA), Curico, Chile, 19–21 October 2016; pp. 1–5.
  6. Ahmad, A.; Anas, M.; Sarwar, A.; Zaid, M.; Tariq, M.; Ahmad, J.; Beig, A.R. Realization of a generalized switched-capacitor multilevel inverter topology with less switch requirement. Energies 2020, 13, 1556.
  7. Ganesh, B.; Murugan, N.; Nallaswamy, M.; Rajkumar, K.; Vijayaraja, L.; Ganesh Kumar, S.; Rivera, M. Implementation of twenty seven level and fifty one level inverter using constant voltage sources. In Proceedings of the 2019 IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies (CHILECON), Valparaiso, Chile, 13–27 November 2019; pp. 1–4.
  8. Vijayaraja, L.; Kumar, S.G.; Rivera, M. A new topology of multilevel inverter with reduced part count. In Proceedings of the 2018 IEEE International Conference on Automation/XXIII Congress of the Chilean Association of Automatic Control (ICA-ACCA), Concepcion, Chile, 17–19 October 2018; pp. 1–5.
  9. Aganah, K.A.; Luciano, C.; Ndoye, M.; Murphy, G. New switched-dual-source multilevel inverter for symmetrical and asymmetrical operation. Energies 2018, 11, 984.
  10. Vijayaraja, L.; Dhanasekar, R.; Balaji, M.; Ganesh Kumar, S. Performance study of 81-level inverter using two stage switch ladder circuit. In Proceedings of the 1st International Science Exhibition Congress Symposium (SECS-2020), Jharkhand, India, 12–13 September 2020.
  11. Ponkumar, S.; Rivera, M.; Kamroon, F.; Kumar, S.G. Realization of cascaded multilevel inverter. In Proceedings of the 2017 CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies (CHILECON), Pucon, Chile, 18–20 October 2017; pp. 1–7.
  12. Hassan, A.; Yang, X.; Chen, W.; Houran, M.A. A state of the art of the multilevel inverters with reduced count components. Electronics 2020, 9, 1924.
  13. Thiyagarajan, V. Simulation analysis of 51-level inverter topology with reduced switch count. Mater. Today Proc. 2020, 33, 3870–3876.
  14. Ali, A.I.M.; Sayed, M.A.; Takeshita, T. Isolated single-phase single-stage DC-AC cascaded transformer-based multilevel inverter for stand-alone and grid-tied applications. Int. J. Electr. Power Energy Syst. 2021, 125, 106534.
  15. Nirmal Mukundan, C.M.; Jayaprakash, P.; Subramaniam, U.; Almakhles, D.J. Trinary hybrid cascaded h-bridge multilevel inverter-based grid-connected solar power transfer system supporting critical load. IEEE Syst. J. 2020.
  16. Rangarajan, P. Investigation of modified multilevel inverter topology for PV system. Microprocess. Microsyst. 2019, 71, 102870.
  17. Zaid, M.M.; Ro, J.-S. Optimal design of a cascaded rectangular-type and circle-type multilevel inverters with a new switching technique. IET Power Electron. 2020, 13, 2831–2846.
  18. Kim, S.-M.; Lee, E.-J.; Lee, J.-S.; Lee, K.-B. An improved phase-shifted DPWM method for reducing switching loss and thermal balancing in cascaded h-bridge multilevel inverter. IEEE Access 2020, 8, 187072–187083.
  19. Sahoo, S.; Ahmed, I. Common mode voltage reduction in NPC multilevel inverter by SVPWM using gh-coordinate system. In Proceedings of the International Conference on Computational Intelligence for Smart Power System and Sustainable Energy (CISPSSE), Keonjhar, Odisha, India, 29–31 July 2020; pp. 1–6.
  20. Sen, P. Novel multilevel inverter based standalone PV System using reduced number of components. In Proceedings of the International Conference on Renewable Energy Integration into Smart Grids: A Multidisciplinary Approach to Technology Modelling and Simulation (ICREISG), Bhubaneswar, India, 14–15 February 2020; pp. 111–115.
  21. Siddique, M.D.; Mekhilef, S.; Shah, N.M.; Sarwar, A.; Iqbal, A.; Memon, M.A. A new multilevel inverter topology with reduce switch count. IEEE Access 2019, 7, 58584–58594.
  22. Joshi, N.R.; Sant, A.V. Analysis of a new symmetric multilevel inverter topology with reduced component count. In Proceedings of the International Conference on Emerging Trends in Information Technology and Engineering (ic-ETITE), Vellore, India, 24–25 February 2020; pp. 1–6.
  23. Ranjbarizad, V.; Aalami, M.; Babaei, E. A new topology for cascaded multilevel inverter to generate more voltage levels with a reduced count of power switches. In Proceedings of the 4th International Conference on Power Electronics and their Applications (ICPEA), Elazig, Turkey, 25–27 September 2019; pp. 1–7.
  24. Kshirsagar, A.; Kaarthik, R.S.; Rahul, A.; Gopakumar, K.; Umanand, L.; Biswas, S.K.; Cecati, C. 17-level inverter with low component count for open-end induction motor drives. IET Power Electron. 2018, 11, 922–929.
  25. Dhanamjayulu, C.; Khasim, S.R.; Padmanaban, S.; Arunkumar, G.; Holm-Nielsen, J.B.; Blaabjerg, F. Design and implementation of multilevel inverters for fuel cell energy conversion system. IEEE Access 2020, 8, 183690–183707.
  26. Kahwa, A.; Obara, H.; Fujimoto, Y. Estimation and analysis of power loss in a reduced switches count H-bridge multilevel inverter. In Proceedings of the IEEE International Conference on Mechatronics (ICM), Ilmenau, Germany, 18–20 March 2019; pp. 25–30.
  27. Rajkumar, K.; Parthiban, P. Performance investigation of transformerless DVR based on T-type multilevel inverter with reduced switch count. In Proceedings of the IEEE International Conference on Sustainable Energy Technologies and Systems (ICSETS), Bhubaneswar, India, 26 February–1 March 2019; pp. 236–241.
  28. Abdoli, H.; Khorsandi, A.; Eskandari, B.; Moghani, J.S. A new reduced switch multilevel inverter for PV applications. In Proceedings of the 11th Power Electronics, Drive Systems, and Technologies Conference (PEDSTC), Tehran, Iran, 4–6 February 2020; pp. 1–5.
  29. Nasiri Avanaki, H.; Barzegarkhoo, R.; Zamiri, E.; Yang, Y.; Blaabjerg, F. Reduced switch-count structure for symmetric multilevel inverters with a novel switched-DC-source submodule. IET Power Electron. 2019, 12, 311–321.
  30. Babaei, E.; Kangarlu, M.F.; Hosseinzadeh, M.A. Asymmetrical multilevel converter topology with reduced number of components. IET Power Electron. 2013, 6, 1188–1196.
  31. Lee, S.S. Single-stage switched-capacitor module (S3CM) topology for cascaded multilevel inverter. IEEE Trans. Power Electron. 2018, 33, 8204–8207.
  32. Majumdar, S.; Mahato, B.; Jana, K.C. Analysis of most optimal multi-unit multi-level inverter having minimum components and lower standing voltage. IETE Tech. Rev. 2020, 1–17.
  33. Ray, S.; Gupta, N.; Gupta, R.A. A comprehensive review on cascaded h-bridge inverter-based large-scale grid-connected photovoltaic. IETE Tech. Rev. 2017, 34, 463–477.
  34. Alishah, R.S.; Hosseini, S.H.; Babaei, E.; Sabahi, M. Optimal design of new cascaded switch-ladder. Multilevel inverter structure. IEEE Trans. Ind. Electron. 2017, 64, 2072–2080.
  35. Umashankar, S.; Sreedevi, T.S.; Nithya, V.G.; Vijayakumar, D. A new 7-level symmetric multilevel inverter with minimum number of switches. Int. Sch. Res. Not. 2013.
  36. Prakash, S.; Kumar, L.; Gupta, S.; Agrawal, N. Implementation of symmetrical multilevel inverter topology. In Proceedings of the IEEE 1st International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES), Delhi, India, 4–6 July 2016; pp. 1–6.
  37. Bharath, K.; Satputaley, R.J. Single phase asymmetrical cascaded multilevel inverter design for induction motor. IJEEDC 2013, 1, 8–13.
  38. Seth, N.; Goel, V.; Kulkarni, R.D.; Joshi, V.P. Performance analysis of seven level three phase asymmetric multilevel inverter at various modulation indices. In Proceedings of the 2016 International Conference on Electrical Power and Energy Systems (ICEPES), Bhopal, India, 14–16 December 2016; pp. 407–413.
  39. Pires, V.F.; Silva, J.F. Hybrid cascade multilevel inverter using a single DC source for open-end winding induction motors. In Proceedings of the 2012 IEEE International Conference on Industrial Technology, Athens, Greece, 19–21 March 2012; pp. 966–970.
  40. Khosroshahi, M.T. Crisscross cascade multilevel inverter with reduction in number of components. IET Power Electron. 2014, 7, 2914–2924.
  41. Oskuee, M.R.J.; Salary, E.; Najafi-Ravadanegh, S. Creative design of symmetric multilevel converter to enhance the circuit’s performance. IET Power Electron. 2015, 8, 96–102.
  42. Wang, L.; Wu, Q.H.; Tang, W. Novel cascaded switched-diode multilevel inverter for renewable energy integration. IEEE Trans. Energy Convers. 2017, 32, 1574–1582.
  43. Alishah, R.S.; Nazarpour, D.; Hosseini, S.H.; Sabahi, M. Novel topologies for symmetric, asymmetric, and cascade switched-diode multilevel converter with minimum number of power electronic components. IEEE Trans. Ind. Electron. 2014, 61, 5300–5310.
  44. Su, G.-J. Multilevel DC-link inverter. IEEE Trans. Ind. Appl. 2005, 41, 848–854.
  45. Liu, J.; Cheng, K.W.E.; Ye, Y. A cascaded multilevel inverter based on switched-capacitor for high-frequency AC power distribution system. IEEE Trans. Power Electron. 2014, 29, 4219–4230.
  46. Gupta, K.K.; Jain, S. A novel multilevel inverter based on switched DC sources. IEEE Trans. Ind. Electron. 2014, 61, 3269–3278.
  47. Mokhberdoran, A.; Ajami, A. Symmetric and asymmetric design and implementation of new cascaded multilevel inverter topology. IEEE Trans. Power. Electron. 2014, 29, 6712–6724.
  48. Arun, N.; Noel, M.M. Crisscross switched multilevel inverter using cascaded semi-half-bridge cells. IET Power Electron. 2018, 11, 23–32.
  49. Ajami, A.; Oskuee, M.R.J.; Mokhberdoran, A.; van den Bossche, A. Developed cascaded multilevel inverter topology to minimise the number of circuit devices and voltage stresses of switches. IET Power Electron. 2014, 7, 459–466.
  50. Thiyagarajan, V.; Somasundaram, P. Multilevel inverter topology with modified pulse width modulation and reduced switch coun. Acta Polytechnica Hungarica 2018, 15, 141–167.
  51. Chappa, A.; Gupta, S.; Sahu, L.K.; Gautam, S.P.; Gupta, K.K. Symmetrical and asymmetrical reduced device multilevel inverter topology. IEEE J. Emerg. Sel. Top. Power Electron. 2019, 9, 885–896.
  52. Ajami, A.; Mokhberdoran, A.; Oskuee, M.R.J. A new topology of multilevel voltage source inverter to minimize the number of circuit devices and maximize the number of output voltage levels. J. Electr Eng Technol. 2013, 8, 1328–1336.
  53. Siddique, M.D.; Mekhilef, S.; Shah, N.M.; Memon, M.A. Optimal design of a new cascaded multilevel inverter topology with reduced switch count. IEEE Access 2019, 7, 24498–24510.
  54. Samadaei, S.E.; Kaviani, M.; Bertilsson, K. A 13-levels module (K-type) with two DC sources for multilevel inverters. IEEE Trans. Ind. Electron. 2019, 66, 5186–5196.
  55. Thiyagarajan, V.; Somasundaram, P.; Ramash Kumar, K. Simulation and analysis of novel extendable multilevel inverter topology. J. Circuits Syst. Comput. 2020, 28, 1950089.
  56. Zeng, J.; Lin, W.; Cen, D.; Liu, J. Novel K-type multilevel inverter with reduced components and self-balance. IEEE J. Emerg. Sel. Top. Power Electron. 2020, 8, 4343–4354.
  57. Loganathan, V.; Srinivasan, G.K.; Rivera, M. Realization of 485 Level Inverter Using Tri-State Architecture for Renewable Energy Systems. Energies 2020, 13, 6627. 
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