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A single-slope analog-to-digital converter (single-slope ADC) is an integrating-type ADC that converts an input analog voltage into a digital word by measuring the time required for a linear ramp waveform to cross the input voltage [1]. The conversion begins with the reset of an integrator capacitor; the integrator then generates a voltage that ramps linearly at a known constant rate while a counter is incremented by a fixed-frequency clock [2]. When the ramp voltage equals the input voltage, a comparator stops the counter, and the counter reading is proportional to the input voltage, yielding the digital output [1]. Because the conversion relies on a single ramp and a single comparison per conversion, the architecture is simple, and its differential linearity is largely determined by the linearity of the ramp generator and the stability of the clock [2]. The single-slope ADC is distinguished from the dual-slope (dual-ramp) ADC, which uses an additional de-integration interval to cancel errors due to ramp slope and component drift [2]. Its conversion time is signal-dependent and relatively long, which places it among low-speed, high-resolution ADC architectures [3].
References
- Allen, P.E.; Holberg, D.R. CMOS Analog Circuit Design, 2nd ed.; Oxford University Press: New York, 2002. ISBN: 9780195107203.
- Maloberti, F. Data Converters; Springer: New York, 2007. ISBN: 978-0-387-32485-2. https://link.springer.com/book/10.1007/978-0-387-32486-9.
- Plassche, R.J. van de. CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 2nd ed.; Kluwer Academic Publishers: Dordrecht, 2003. ISBN: 9781475737684.
