The cubic silicon carbide is the only polytype that can be grown on silicon wafers. This approach reduces the cost as no SiC substrate is used and only the silicon carbide layer thickness required for the specific application is grown on a cheaper Si substrate. This technology also offers the potential for faster scale-up with wafer size compared with the development of larger diameter hexagonal SiC wafers. In principle, with a large reactor, a 300 mm Si wafer can be obtained using the present process.
Wide band-gap (WBG) semiconductor devices based on both silicon carbide (SiC) and gallium nitride (GaN) can lead a revolution in power electronics through its faster switching speeds, lower losses, and higher blocking voltages . Furthermore, their properties enable higher operating temperatures and increased power densities, but until now the benefits shown by WBG power electronics have not been fully realized due to the high costs of the material and reliability challenges.
Silicon carbide is a material presenting different crystalline structures called polytypes . To date, only the two hexagonal structures 4H and 6H-SiC are commercialized, while the cubic form (3C-SiC) is not used until now in power devices despite the large effort of the last years and several hundreds of papers published for each year. All these polytypes have similar benefits over silicon such as higher breakdown fields (2–4 MV/cm) and the larger energy band-gap (2.3–3.2 eV).
Both 3C-SiC and GaN can work in the same breakdown voltage range (200–1200 V). 3C-SiC is more appropriate for high-current applications due to its high thermal conductivity, while GaN better fits in RF applications because of the high saturated electron velocity. The lower band-gap of 3C-SiC (2.3 eV) in comparison to 4H-SiC (3.28 eV) is often viewed as a negative aspect with respect to other polytypes. The lower band-gap brings a positive effect because the lowering of the conduction band minimum causes a reduced density of states at the SiO 2/3C-SiC interface . As a consequence, it has been demonstrated that the metal oxide semiconductor field effect transistor (MOSFET) on 3C-SiC has the highest channel mobility (above 300 cm 2/V/s) ever presented on any SiC polytype . This produces a large reduction in the power consumption of power switching devices . A remaining challenge in both 3C and 4H-SiC is the electrical activity of extended defects. It is identified as the major problem for electronic device functionality. The mechanisms of defect formation must be clarified and the methods for their reduction developed to reach full functionality and high yield . So far, the growth of 3C-SiC on silicon has been demonstrated on 150 mm Si wafers . The process is feasible with up-scaled reactors on 200 mm or 300 mm wafers.
In the CHALLENGE project, two main different approaches were used to grow 3C-SiC. From one hand, several compliance substrates (pillars, SiGe buffer layer, ISP, etc.) were used to reduce both defects and stress. On the other hand, new bulk growth techniques (PVT or CVD) have been developed to improve the quality of this material. During this work, a new understanding of the defects in this material (protrusions, APBs, SFs, and point defects), their interactions, and the effect of the growth process on their formation and reduction have been obtained. This new understanding has been also helped by the simulation codes developed inside the project (KMCsL, MD, phase field, etc.) and by new characterization techniques (C-AFM).
From this large study on the growth of 3C-SiC, several conclusions can be reported: The use of the SiGe buffer layer is interesting and in some cases, some good quality samples can be obtained. The main limitation is that a low-temperature growth should be used and the Ge segregation at the 3C-SiC/Si interface can produce the formation of polycrystalline regions. The process window is narrow and thus this process can be difficult to use in a production line. The ISP substrate produces a fast decrease of the SFs’ density, as reported in the previous papers, but at the same time produces the formation of APBs that can be detrimental for the leakage current of the devices, as observed by C-AFM measurements. To decrease the APBs concentration, a very high thickness can be grown or new ISP structures should be realized. The pillar substrates have demonstrated to be extremely interesting in reducing the stress and bow of the wafer, especially for (111) substrates. On this kind of substrate, even 25–30 μm of the 3C-SiC layer could be grown without cracks and with a low bow. The main problem of this process is that the 3D growth of 3C-SiC is not easy to control and thick layers are needed to obtain a continuous substrate. This kind of technology can be interesting in the future when a good 3C-SiC (111) layer should be realized. During the last years, we developed a carbonization process that decreases the voids almost to zero at the 3C-SiC/Si interface with a considerable improvement of the material quality and a decrease of the stress. Even the growth during the temperature ramp (buffer layer) between the carbonization and growth steps has a large effect on the stress. The main part of the investigation of the last years has been on the study of the evolution of SFs and APBs, as well as their interactions. The different types of SFs (SF<1>, SF<2>, SF<3>), their generation and annihilation, and the influence of the PD on these processes have been observed and studied in great detail. Another aspect that has been studied in detail is the interaction between the APBs and SFs. In fact, APBs can both generate or annihilate SFs and all these processes have been studied both experimentally and by simulations. It has been observed that due to this equilibrium between the generation and recombination of SFs, very thick layers are needed to obtain a low value of SFs that can provide the opportunity to realize a good device on 3C-SiC. The growth conditions (growth temperature, growth rate, and doping) can influence this equilibrium between generation and annihilation. It seems also that the different types of SFs have different behaviors during the growth but more investigations on this aspect are needed. From these studies, it has been understood that the bulk growth of 3C-SiC is needed to obtain a low value of defects compatible with the realization of power devices. We have developed different kinds of growth techniques (CVD and PVT) to realize bulk wafers with dimensions compatible with the actual standards (100 and 150 mm) but the main problem is related to the formation of the protrusions in the first instant of the growth. This 3D defect can grow and cover the entire surface of the ingot, thus a new process that can eliminate the formation of these defects is needed to obtain a 3C-SiC wafer for the realization of power devices. Another aspect of the 3C-SiC bulk growth that needs further investigation is the intrinsic stress of this material. In fact, the high level of stress and bow of the wafers are a problem for the further processing of the 3C-SiC wafers.
Further work should be done to obtain a good material for power devices, but the work performed during this project is a fundamental step for developing new materials for power devices.