Table of Contents

    Topic review

    Switched-Biasing Techniques for CMOS VCO

    View times: 12
    Submitted by: Jong-Ryul Yang

    Definition

    A voltage-controlled oscillator (VCO) is a key component to generate high-speed clock of mixed-mode circuits and local oscillation signals of the frequency conversion in wired and wireless application systems. In particular, the recent evolution of new high-speed wireless systems in the millimeter-wave frequency band calls for the implementation of the VCO with high oscillation frequency and low close-in phase noise. The effect of the flicker noise on the phase noise of the VCO should be minimized because the flicker noise dramatically increases as the deep-submicron complementary metal-oxide-semiconductor (CMOS) process is scaled down, and the flicker corner frequency also increases, up to several MHz, in the up-to-date CMOS process. 

    1. Introduction

    A voltage-controlled oscillator (VCO) is a key component in a frequency synthesizer that generates local oscillator (LO) signals for frequency conversion in a radio-frequency (RF) transceiver[1][2][3]. A VCO-based readout circuit, which is that the output voltage of the sensing core is applied to the node of the VCO tuning voltage, has merit to achieve a low sensitivity level and a high signal-to-noise ratio compared to the amplifier-based readout circuit[4][5]. In addition, high integration and low power consumption of the VCO-based readout circuit are advantageous for implementing a large-scale sensor array [6][7]. Radar sensors that monitor the change of electromagnetic-wave between the transmitted and received signals generated from the VCO remotely measure the distance, velocity, and vital-signs in real time[8][9][10]. Various sensors using VCOs require low phase noise characteristics in VCOs [11][12][13]. The frequency synthesizer such as the phase-locked loop (PLL) is conventionally used to reduce the phase noise, but the noise characteristics still remain at the output signal of the frequency synthesizer because the loop bandwidth of the PLL in the synthesizer is generally determined to be between 100 and 500 kHz[14][15].

    A complementary metal-oxide-semiconductor (CMOS) process is a standard fabrication technology to implement electrical circuits; it can integrate control, logic, analog, and RF circuits into a single-chip system[16]. Moreover, the recent CMOS device designed in the several nanometer-scale shows competitive performances in transconductance (gm) and minimum noise figure (NFmin), compared to the compound semiconductor device[17]. However, the transistor device implemented in the up-to-date CMOS process exhibits an increase in the flicker noise, which intrinsically depends on the physical structure of the channel and the flicker corner frequency, where the magnitudes of the flicker and white noises present equal increases up to several MHz or more[18][19]. The flicker noise is called “1/f noise” because the noise is increased as the frequency in the channel decreases[20]. The nanometer-scaled CMOS technology has advantages such as high integration, low power consumption, and high operating frequency, but it has the disadvantage of noise deterioration in the low-frequency band owing to the increase in the flicker noise[14].

    The reduction in the flicker noise is a major issue in VCO design using the CMOS process because the phase noise of the VCO is mainly determined by the noise in the low-frequency region[21]. Many studies have been conducted to improve the reduction in the CMOS VCO phase noise performance caused by the flicker noise. Biasing techniques for core transistors have been widely used to prevent the degradation of the VCO phase noise by the flicker noise of the oscillator core transistors[22][23]. A VCO using core transistors biased at class C operation is a representative technique that reduces the contribution of the flicker noise effect from the core transistor at the output[24][25][26]. A resonant filter at the second harmonic also minimizes the noise effect from the core transistors, but the large chip size and the tuning range limit cause other issues in the design of the VCO using this technique[27]. The increase in the chip area can be reduced by implementing the filter using the common-mode resonance of the LC tank in a cross-coupled LC oscillator, although the issue of the tuning range limit cannot be solved[15][28][29]. The performance degradation by the noise of the core transistors is reduced by these techniques, but the contribution of the flicker noise caused by the current source, which is used to constantly supply the DC bias current in the core transistors, remains in the output characteristics of the VCO. The flicker noise by the current source dramatically increases the close-in phase noise of the VCO owing to the nonlinear characteristics of the VCO[30]. A simple method to reduce the effect of the flicker noise from the transistors constituting the current source is to design the VCO using only voltage biasing, that is, without using any current sources[14][31]. However, the core current of the VCO can easily deviate from the designed value depending on the power supply variations when current biasing is not used. It can also be observed that the oscillator becomes more sensitive to ground noise[21]. A switched-biasing technique has been proposed to reduce the flicker noise effect of the current source based on the periodic behavior of the differential VCO[32][33]. The up-conversion behavior of the flicker noise of the current source can be fundamentally eliminated using the switched-biasing technique, which is based on the periodic operation of the differential VCO[34].

    2. Switched-Biasing Technique

    As the deep-submicron CMOS process is scaled down, the low-frequency noise (especially the flicker noise) of the MOSFET becomes more important in the design of CMOS RF transceivers. It has long been known that the flicker noise is generated in a variety of homogeneous semiconductor bulks and is observed in various devices, such as a vacuum tube, diode, and MOSFET[35][36]. Various research works have been conducted to identify the cause of the flicker noise and to clearly understand its characteristics clearly [32][33][34][35][36][37][38][39][40][41][42][43]. To predict the flicker noise phenomenon generated in MOSFETs, Hooge published a carrier mobility fluctuation (CMF) model, in which the flicker noise is caused by the mobility fluctuation of free carriers in the device[37]. McWhorter suggested a carrier number fluctuation (CNF) model, where the low frequency noise of the MOSFET is generated by the fluctuation in the number of charge carriers in the device[38]. The two presented models were useful for understanding the physical mechanism of the flicker noise, but their limitation is that they can only be applied to the long-channel devices. The flicker noise in short-channel devices is mainly considered to be due to the random telegraph signal (RTS) noise generated by the Si−SiO2 interface because as the size of the devices is scaled down, the device operation is predominantly represented by the movement of each charge carrier[39][41][44].

    Research on reducing the intrinsic flicker noise of MOSFETs began in the early 1990s. Bloom and Nemirovsky first suggested that the flicker noise of the MOSFET could be reduced by cycling between inversion and accumulation of the device[40]. They explained that the device noise in the on-state can be reduced when the off-state exists before the on-state. Dierickx and Simoen revealed that the flicker noise reduction by inversion-to-accumulation cycling is related to the emptying of traps at the interface that generates RTS noise[41]. Based on the principle of inversion-to-accumulation cycling, Gierkink et al. proposed a switched-biasing technique[32]Figure 1 shows the operating principle of the switched-biasing technique[33]. The “operational state” in Figure 1 means that the MOSFET operates at the inversion state, to facilitate the flow of current between the drain and the source. The drain–source current does not flow at the “rest-state” of the MOSFET because the bias voltage at the gate is lower than the threshold voltage of the device. A reduction in the flicker noise can be expected by the periodic operation between the two states of the device and is verified with a simple mathematical analysis. Assuming a duty cycle of 50%, the drain–source current of the MOSFET by the switching operation can be expressed as the multiplication of the flicker noise and a square-wave signal m(t) with the duty cycle,

    where ωsw is the angular frequency of the switching operation. Because the power spectral density (PSD) of the noise in the low-frequency band is determined by the convolution of the DC component of m(t) and the flicker noise, the switched-biasing technique can decrease the PSD by 6 dB compared to the constant-biasing technique. In addition, several studies have confirmed that the flicker noise is further reduced when the transistor is sufficiently turned off (i.e., deep accumulation). This reduction is known to be caused by the elimination of the long-term-memory effect associated with the flicker noise[32][33][44] The analysis of the operating characteristics and principle shows that the PSD due to low-frequency noise depends on the bias state at the time and the bias history in a periodic operation [44]. This phenomenon was verified in both NMOS and PMOS because the carrier type does not affect the operating principle[43].

    Figure 2. Schematic of a CMOS LC-VCO with the switched-biasing technique to the current source (reproduced with permission from the author, RF CMOS low-phase-noise LC oscillator through memory reduction tail transistor; published by IEEE, 2004)[34].

    The characteristics that the current source modulated by the switched-biasing technique is effective in improving the phase noise of a VCO was proved using a theoretical analysis based on a mathematical model[47]. The proposed theoretical analysis is based on the impulse sensitivity function (ISF) theory, which can explain the phase noise contribution depending on the output voltage swing of the VCO. The proposed analysis in Figure 3 shows that the phase noise of a VCO can be greatly improved by additionally injecting the bias current to the VCO core transistors at the time when the voltage swing of the VCO is maximized or minimized. This phenomenon is based on the fact that the time when the output voltage of the VCO becomes the maximum or minimum has the minimum sensitivity to the phase shift[47]Figure 3b shows that the phase noise of the VCO can be minimized by the modulation signals of 2f0 in the current source compared to the fixed-biasing current source. It is caused that the bias currents of the cross-coupled transistors in the VCO using the switched-biasing current source are limited at a time of high phase-shift sensitivity and supplied at a time of low phase-shift sensitivity. The currents Id1 and Id2 supplied from the switched biasing current source are not supplied at the highly sensitive time in the phase noise where the output voltages Vo,n and Vo,p are crossed. Based on physical and theoretical interpretations, it can be verified that the switched-biasing technique improves the phase noise of the VCO by modulating the current source.

    Figure 3. Analysis of VCO characteristics depending on the pulse modulation of the current source using the impulse sensitivity function theory: (a) schematic of the differential LC-VCO; (b) conceptual waveforms of the output voltages and drain currents of the VCO and the bias current by the pulse-modulated current source (reproduced with permission from the author, Tail current-shaping to improve phase noise in LC voltage-controlled oscillators; published by IEEE, 2006)[47].

    The entry is from 10.3390/s21010316

    References

    1. Jann, B.; Chance, G.; Roy, A.G.; Balakrishnan, A.; Karandikar, N.; Brown, T.; Li, X.; Davis, B.; Ceballos, J.L.; Tanzi, N.; et al. 21.5 A 5G Sub-6GHz Zero-IF and mm-Wave IF Transceiver with MIMO and Carrier Aggregation. In Proceedings of the 2019 IEEE International Solid- State Circuits Conference—(ISSCC), San Francisco, CA, USA, 17–21 February 2019; pp. 352–354.
    2. Khalaf, K.; Vaesen, K.; Brebels, S.; Mangraviti, G.; Libois, M.; Soens, C.; Thillo, W.V.; Wambacq, P. A 60-GHz 8-Way Phased-Array Front-End With T/R Switching and Calibration-Free Beamsteering in 28-nm CMOS. IEEE J. Solid-State Circuits 2018, 53, 2001–2011.
    3. Dunworth, J.D.; Homayoun, A.; Ku, B.; Ou, Y.; Chakraborty, K.; Liu, G.; Segoria, T.; Lerdworatawee, J.; Park, J.W.; Park, H.; et al. A 28GHz Bulk-CMOS Dual-Polarization Phased-Array Transceiver with 24 Channels for 5G User and Basestation Equipment. In Proceedings of the 2018 IEEE International Solid—State Circuits Conference—(ISSCC), San Francisco, CA, USA, 11–15 February 2018; pp. 70–72.
    4. Angevare, J.; Pedalà, L.; Sönmez, U.; Sebastiano, F.; Makinwa, K.A.A. A 2800-μm2 Thermal-Diffusivity Temperature Sensor with VCO-Based Readout in 160-nm CMOS. In Proceedings of the 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), Xiamen, China, 9–11 November 2015; pp. 1–4.
    5. Enache, A.; Drăghici, F.; Pristavu, G.; Brezeanu, G. Voltage Controlled Oscillator for Small-Signal Capacitance Sensing. In Proceedings of the 2019 International Semiconductor Conference (CAS), Sinaia, Romania, 9–11 October 2019; pp. 323–326.
    6. Quintero, A.; Cardes, F.; Perez, C.; Buffa, C.; Wiesbauer, A.; Hernandez, L. A VCO-Based CMOS Readout Circuit for Capacitive MEMS Microphones. Sensors 2019, 19, 4126.
    7. Vornicu, I.; Carmona-Galán, R.; Rodríguez-Vázquez, Á. Arrayable Voltage-Controlled Ring-Oscillator for Direct Time-of-Flight Image Sensors. IEEE Trans. Circuits Syst. Regul. Pap. 2017, 64, 2821–2834.
    8. Tseng, S.; Kao, Y.; Peng, C.; Liu, J.; Chu, S.; Hong, G.; Hsieh, C.; Hsu, K.; Liu, W.; Huang, Y.; et al. A 65-nm CMOS Low-Power Impulse Radar System for Human Respiratory Feature Extraction and Diagnosis on Respiratory Diseases. IEEE Trans. Microw. Theory Tech. 2016, 64, 1029–1041.
    9. Park, J.-H.; Yang, J.-R. Two-Tone Continuous-Wave Doppler Radar Based on Envelope Detection Method. Microw. Opt. Technol. Lett. 2020, 62, 3146–3150.
    10. Sim, J.Y.; Park, J.-H.; Yang, J.-R. Vital-Signs Detector Based on Frequency-Shift Keying Radar. Sensors 2020, 20, 5516.
    11. Bassi, M.; Caruso, M.; Bevilacqua, A.; Neviani, A. A 65-nm CMOS 1.75–15 GHz Stepped Frequency Radar Receiver for Early Diagnosis of Breast Cancer. IEEE J. Solid-State Circuits 2013, 48, 1741–1750.
    12. Tu, C.; Wang, Y.; Lin, T. A Low-Noise Area-Efficient Chopped VCO-Based CTDSM for Sensor Applications in 40-nm CMOS. IEEE J. Solid-State Circuits 2017, 52, 2523–2532.
    13. Peng, K.; Chen, S.; Wang, F.; Horng, T. Enhancement of Vital-Sign Sensor Signal-to-Noise Ratio Using Wireless Frequency-Locked Loop. In Proceedings of the 2019 IEEE SENSORS, Montreal, QC, Canada, 27−30 October 2019; pp. 1–3.
    14. Pepe, F.; Bonfanti, A.; Levantino, S.; Samori, C.; Lacaita, A.L. Analysis and Minimization of Flicker Noise Up-Conversion in Voltage-Biased Oscillators. IEEE Trans. Microw. Theory Tech. 2013, 61, 2382–2394.
    15. Hu, Y.; Siriburanon, T.; Staszewski, R.B. A Low-Flicker-Noise 30-GHz Class-F23 Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path. IEEE J. Solid-State Circuits 2018, 53, 1977–1987.
    16. Tang, K.; Lou, L.; Guo, T.; Chen, B.; Wang, Y.; Fang, Z.; Yang, C.; Wang, W.; Zheng, Y. A 4TX/4RX Pulsed Chirping Phased-Array Radar Transceiver in 65-nm CMOS for X-Band Synthetic Aperture Radar Application. IEEE J. Solid-State Circuits 2020, 55, 2970–2983.
    17. Bennett, H.; Brederlow, R.; Costa, J.; Cottrell, P.; Huang, W.; Immorlica, A.; Mueller, J.-E.; Racanelli, M.; Shichijo, H.; Weitzel, C.; et al. Device and Technology Evolution for Si-Based RF Integrated Circuits. IEEE Trans. Electron Devices 2005, 52, 1235–1258.
    18. Razavi, B. RF Microelectronics (2nd Edition) (Prentice Hall Communications Engineering and Emerging Technologies Series), 2nd ed.; Prentice Hall Press: Upper Saddle River, NJ, USA, 2011; ISBN 978-0-13-713473-1.
    19. Nemirovsky, Y.; Corcos, D.; Brouk, I.; Nemirovsky, A.; Chaudhry, S. 1/f Noise in Advanced CMOS Transistors. IEEE Instrum. Meas. Mag. 2011, 14, 14–22.
    20. Leeson, D.B. A Simple Model of Feedback Oscillator Noise Spectrum. Proc. IEEE 1966, 54, 329–330.
    21. Bevilacqua, A.; Andreani, P. An Analysis of 1/f Noise to Phase Noise Conversion in CMOS Harmonic Oscillators. IEEE Trans. Circuits Syst. Regul. Pap. 2012, 59, 938–945.
    22. Hu, Y.; Siriburanon, T.; Staszewski, R.B. Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased Oscillators. IEEE Trans. Circuits Syst. II Express Briefs 2019, 66, 1962–1966.
    23. Franceschin, A.; Andreani, P.; Padovan, F.; Bassi, M.; Bevilacqua, A. A 19.5-GHz 28-nm Class-C CMOS VCO, with a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects. IEEE J. Solid-State Circuits 2020, 55, 1842–1853.
    24. Mazzanti, A.; Andreani, P. Class-C Harmonic CMOS VCOs, With a General Result on Phase Noise. IEEE J. Solid-State Circuits 2008, 43, 2716–2729.
    25. Deng, W.; Okada, K.; Matsuzawa, A. Class-C VCO With Amplitude Feedback Loop for Robust Start-Up and Enhanced Oscillation Swing. IEEE J. Solid-State Circuits 2013, 48, 429–440.
    26. Hong, C.-H.; Wu, C.-Y.; Liao, Y.-T. Robustness Enhancement of a Class-C Quadrature Oscillator Using Capacitive Source Degeneration Coupling. IEEE Trans. Circuits Syst. II Express Briefs 2015, 62, 16–20.
    27. Hegazi, E.; Sjoland, H.; Abidi, A.A. A Filtering Technique to Lower LC Oscillator Phase Noise. IEEE J. Solid-State Circuits 2001, 36, 1921–1930.
    28. Murphy, D.; Darabi, H. 2.5 A Complementary VCO for IoE That Achieves a 195 dBc/Hz FOM and Flicker Noise Corner of 200 kHz. In Proceedings of the 2016 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 31 January−4 February 2016; pp. 44–45.
    29. Guo, H.; Chen, Y.; Mak, P.; Martins, R.P. 26.2 A 0.08 mm2 25.5-to −29.9 GHz Multi-Resonant-RLCM-Tank VCO Using a Single-Turn Multi-Tap Inductor and CM-Only Capacitors Achieving 191.6 dBc/Hz FoM and 130 kHz 1/f3 PN Corner. In Proceedings of the 2019 IEEE International Solid- State Circuits Conference—(ISSCC), San Francisco, CA, USA, 17−21 February 2019; pp. 410–412.
    30. Rael, J.J.; Abidi, A.A. Physical Processes of Phase Noise in Differential LC Oscillators. In Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No. 00CH37044), Orlando, FL, USA, 24 May 2000; pp. 569–572.
    31. Shahmohammadi, M.; Babaie, M.; Staszewski, R.B. A 1/f Noise Upconversion Reduction Technique for Voltage-Biased RF CMOS Oscillators. IEEE J. Solid-State Circuits 2016, 51, 2610–2624.
    32. Gierkink, S.L.J.; Klumperink, E.A.M.; van der Wel, A.P.; Hoogzaad, G.; van Tuijl, E.A.J.M.; Nauta, B. Intrinsic 1/f Device Noise Reduction and Its Effect on Phase Noise in CMOS Ring Oscillators. IEEE J. Solid-State Circuits 1999, 34, 1022–1025.
    33. Klumperink, E.A.M.; Gierkink, S.L.J.; van der Wel, A.P.; Nauta, B. Reducing MOSFET 1/f Noise and Power Consumption by Switched Biasing. IEEE J. Solid-State Circuits 2000, 35, 994–1001.
    34. Boon, C.C.; Do, M.A.; Yeo, K.S.; Ma, J.G.; Zhang, X.L. RF CMOS Low-Phase-Noise LC Oscillator through Memory Reduction Tail Transistor. IEEE Trans. Circuits Syst. II Express Briefs 2004, 51, 85–90.
    35. Hooge, F.N. 1/f Noise. Phys. BC 1976, 83, 14–23.
    36. Keshner, M.S. 1/f Noise. Proc. IEEE 1982, 70, 212–218.
    37. Hooge, F.N. 1/ƒ Noise Is No Surface Effect. Phys. Lett. A 1969, 29, 139–140.
    38. McWhorter, A.L. 1/f Noise and Related Surface Effects in Germanium. Ph.D. Thesis, Massachusetts Institute of Technology, Cambridge, MA, USA, 1955.
    39. Kirton, M.J.; Uren, M.J. Noise in Solid-State Microstructures: A New Perspective on Individual Defects, Interface States and Low-Frequency (1/ƒ) Noise. Adv. Phys. 1989, 38, 367–468.
    40. Bloom, I.; Nemirovsky, Y. 1/ f Noise Reduction of Metal-oxide-semiconductor Transistors by Cycling from Inversion to Accumulation. Appl. Phys. Lett. 1991, 58, 1664–1666.
    41. Dierickx, B.; Simoen, E. The Decrease of ‘“Random Telegraph Signal”’ Noise in Metal-oxide-semiconductor Field-effect Transistors When Cycled from Inversion to Accumulation. J. Appl. Phys. 1992, 71, 2028–2029.
    42. van der Wel, A.P.; Klumperink, E.A.M.; Gierkink, S.L.J.; Wassenaar, R.F.; Wallinga, H. MOSFET 1/f Noise Measurement under Switched Bias Conditions. IEEE Electron Device Lett. 2000, 21, 43–46.
    43. Kolhatkar, J.S.; Salm, C.; Knitel, M.J.; Wallinga, H. Constant and Switched Bias Low Frequency Noise in p-MOSFETs with Varying Gate Oxide Thickness. In Proceedings of the 32nd European Solid-State Device Research Conference, Firenze, Italy, 24−26 September 2002; pp. 83–86.
    44. van der Wel, A.P.; Klumperink, E.A.M.; Kolhatkar, J.S.; Hoekstra, E.; Snoeij, M.F.; Salm, C.; Wallinga, H.; Nauta, B. Low-Frequency Noise Phenomena in Switched MOSFETs. IEEE J. Solid-State Circuits 2007, 42, 540–550.
    45. Koh, J.; Schmitt-Landsiedel, D.; Thewes, R.; Brederlow, R. A Complementary Switched MOSFET Architecture for the 1/f Noise Reduction in Linear Analog CMOS ICs. IEEE J. Solid-State Circuits 2007, 42, 1352–1361.
    46. Kim, J.; An, H.; Yun, T. A Low-Noise WLAN Mixer Using Switched Biasing Technique. IEEE Microw. Wirel. Compon. Lett. 2009, 19, 650–652.
    47. Soltanian, B.; Kinget, P.R. Tail Current-Shaping to Improve Phase Noise in LC Voltage-Controlled Oscillators. IEEE J. Solid-State Circuits 2006, 41, 1792–1802. 
    More