Cockcroft and Walton (1932), at the Cavendish Laboratory in Cambridge, England, needed higher particle energies to accelerate sub-atomic particles along a straight discharge tube. A voltage multiplier circuit designed using a stack of capacitors connected to diodes acting as switches. By asserting and de-asserting the switches in proper sequence, they built up a potential of 800 kV ^[1]. This voltage multiplier circuit was far lighter and cheaper than transformers. Cockroft and Walton designed a voltage multiplier, which converted low AC power or DC pulses to a higher DC voltage level as shown in Figure 1. In this design, capacitors were connected in series, where diodes were employed to produce high voltage.

Figure 1. Schematic diagram of Cockcroft–Walton voltage multiplier ^[1].

Moreover, this scheme eliminated the heavy core as transformers did. In this method, the bulk of insulation/potting is required. A higher voltage was achieved from a low supply voltage using these capacitors and diodes as a multiplier. It had the advantage of low-cost materials requirement with an easy setup method ^[2]. However, this scheme suffered from some drawbacks; if the number of stages increased, then the higher stage’s voltage started to “sag” due to capacitors’ electrical impedance and the small number of steps. Moreover, when the output current is injected, a large voltage ripple is produced to increment the stages.

Dickson (1976) used the same concept as the Cockcroft–Walton voltage multiplication circuit and implemented it in IC’s. It was very similar to the CP voltage multiplier, where the diode-connected chains are coupled to the input through several capacitors connected in parallel. Therefore, all the capacitors needed to withstand storing the full voltages produced by these chains. The system could achieve efficient multiplication by involving many capacitors. However, involving many capacitors in the circuitry increased the power dissipation and decreased pumping efficiency ^[3]. The primary Dickson CP circuit was very robust with different high voltage generation issues until sub-micron design technology. When the diode-connected MOSFET was turned on in the Dickson CP circuit, the threshold voltage was the voltage difference between the drain and source terminal of the diode-connected MOSFET. The conventional Dickson CP circuit structure had a low pumping capacity due to the large threshold voltage and the body-effect in each stage to generate the high voltages as shown in Figure 2. Additionally, all the steps suffered from a high-voltage overstress and a voltage difference, which was 2xVDD in each node caused by each node’s gate oxides. Consequently, when the number of pumping stages increases, the body effect degrades the Dickson CP circuit’s pumping efficiency.

Figure 2. Dickson charge pump (CP) circuit with diode-capacitor ^[3].

Dickson CP circuit could not generate the desired output voltage as it was suffering from the body effect on the diode-connected MOSFETs. Therefore, Witters et al. (1989) proposed a new mechanism for designing a triple-well process CP ^[4]. In complementary metal-oxide-semiconductor (CMOS) circuit design, voltage multiplier circuits used a transistor, which performed as diodes. However, threshold voltage arises to the transistor in this circuit’s chain due to the body effect problem the performance affected slightly. The output voltage level could not meet the requirements compared to a diode configuration, which eventually reduced the circuit’s internal resistance. This difference between these methods got worse when any circuit implementation required more stages. Any multiplier or boosting circuit’s output voltage was limited, regardless of the necessary number of steps.

Moreover, the substrate current produced in the floating-well technique affects other circuits in the same chip. Therefore, this scheme for multiplying circuit was proposed and verified for implementation. Nevertheless, this technique predicted the characteristics of a wide variety of voltage multipliers.

Atsumi et al. (1994) designed a striking and widely-implemented CP circuit named bootstrap CP. In this scheme, a simple MOS transistor or transmission gate have utilized as a switching terminal to generate higher voltage than the power supply voltage. Therefore, the MOS transistor has to switch on with a suitable supply voltage to the gate terminal, higher than the source terminal voltage. These required high gate voltages were attained from each stage to another capacitor and MOS transistor, forming the bootstrap circuit. Though the circuit generated higher output voltage, it is also clear from the complex circuit structure that it required higher implementation cost for a more complex clocking scheme and control section, which has four phases and double amplitude of the supply voltage ^[5][6].

3. CP for Memory Application

Lauterbach et al. (2000) illustrated a novel idea of power saving in boosted CP circuits, which doubles the power efficiency by integrating two-step adiabatic switching, charge sharing, and a simplified clocking arrangement. As this scheme shares the charges, so clock driver strengths declined. Therefore, the maximum value of the charging current dropped by a factor of three. On the other hand, combining the tri-state drivers and the clocking circuits removed the parasitic charge current peaks. As a result, the electromagnetic emission of the CP circuit condensed considerably. However, the charge-sharing concept necessitates this external clock generator to pump the voltage, ultimately increasing power dissipation ^[7].

Lai and Wang (2001) proposed a CP circuit where source-bulk-connected techniques were utilized with two associated courses, which solved the limitation of charge sharing methods. These circuits are involved in the primary CP circuit to reduce the body effect while avoiding the forward-biased PN junction. The body of each charge transfer transistor in the primary pumping circuit is connected to the body bias circuit. When pumping begins, the CP circuit draws the current from CL and the internal node voltage becomes lower. However, in the source-bulk connected techniques, the large bulk-to-well PN-junction capacitance increased the parasitic capacitance at each pumping node. Second, to control the diode-connected MOSFETs’ body terminals dynamically, auxiliary MOSFETs are used in the source-bulk scheme, which generated the substrate current floating-well devices. However, using these extra circuitries caused large power dissipation with a large chip area ^[8].

Tanzawa et al. (2002) proposed a CP based on Umezawa et al.’s design principle. The proposed CP configuration required several logic circuits and PC2 switches. In this design, an additional circuit is added, which reduces the number of PC1 elements to only four. Moreover, most of the capacitors in the PC1 scheme only added a 10% increment of the total area in the PC2 method. Additionally, in this design, only high voltage transistors are included with intrinsic capacitors ^[9].

Pelliconi et al. (2003) proposed a power-efficient charge pump in 2003, including low-voltage transistors and a simple two-phase clocking scheme. In this method, higher operating clocks have engaged compared to other conventional methods. As a result, it has obtained high-current, high-efficiency and small-chip area. Around 100 MHz clock frequency has been received from the measured results. However, the circuit has secured fast switching times on low resistance and low capacitors. However, the circuit could not manage higher efficiency and boosted output voltage ^[10].

In 2005, Yan and Min proposed a CP method based on all P-channel metal–oxide–semiconductor (PMOS) transistors, suitable for the standard CMOS process. In this scheme, only low voltage PMOS transistors are used with the switching substrate technique to boost the transistors. Moreover, in this design, body effects have been eliminated to increase the output voltage and threshold voltage loss. This body effect was also reduced by employing the linear operation of PMOS based charge transfer switches. Therefore, this scheme has become compatible with low voltage memory applications. However, using all the PMOS transistors for transferring charge from one stage to another substrate current increased, resulting in higher power dissipation ^[11].

In 2008, Su and Ma proposed a four-phase CP circuit to reduce the reversion and conduction loss in each step. In this scheme, the voltage drop method is reduced in each sub-cell during the power stage. As a result, higher efficiency has been achieved with a low ripple and lower fabrication cost. Moreover, involving a subthreshold clock generator reduced the power loss in the controller. Therefore, it has provided an effective solution to the applications related to low voltage and low-power system-on-chip power converters. However, due to many capacitors, the proposed CP is not entirely free from parasitic effects ^[12].

Richelli et al. presented two CP methods for NVM with dynamic biasing of the gate and the body voltages. In this scheme, the device voltage loss problem created due to the device threshold has been controlled through gate and body biasing of every pass transistor. By using this scheme, a charge was pumped with minimal voltage drop and high conductivity. This scheme provided higher output voltage and pumping efficiency with involving only a two-phase clocking scheme. However, this design occupied a large chip area due to two pumping stages ^[13][14][15].

4. CP for DC–DC Converter

Shiau et al. (2007) implemented a polysilicon diode-based low voltage CP. There is no limitation of the boosted output voltage in this scheme, as polysilicon diodes are fully isolated from the silicon substrate as shown in Figure 3. Moreover, in this design method, CP is not limited by MOSFETs junction breakdown voltage, which can implement in a standard CMOS process. However, in this scheme, the body effect has not been eliminated, which is the main disadvantage of a diode-based CP circuit ^[16].

Huang et al. proposed a CP circuit based on dual-phase mode ^[17]. In this scheme, several phases have been observed with the completely compact CP circuit with multiphase current-mode control. This structure involved the sensor stage, the buffer stage, the power stage, the automatic body switching (ABS) circuit, and the non-overlap circuit. The proposed structure claimed to have low ripple voltage, small chip area with high system stability. However, due to several phases, parasitic capacitance and resistance effect have not been controlled correctly in this structure.

In 2010, Peng et al. proposed a CTS-based CP circuit, where auxiliary capacitors and transistors were used to dynamically bias the CTSs to the influence of the switch’s threshold voltage transistor. Moreover, this design aims to improve the pumping efficiency and lower the threshold voltage when it is turned on during charge transfer and acquires higher when turned off ^[18]. However, the power dissipation was high, and the pumping efficiency or voltage gain was still lower owing to the complex switching mechanism.

To remove the body effect of the diode-connected CP circuit and direct the flow of charges in pumping operation, MOSFET switches with proper on/off cycles, referred to as charge transfer switch (CTS) used to design the charge pump circuit. The CTS was able to produce better pumping gain than the diodes. Many researchers developed the CP with CTS, which required an auxiliary pass transistor to turn off the CTS entirely in the designated period ^[19]. Dong-Sheng et al. (2006) designed a CP circuit using the CTS topology, which had parasitic capacitors at each pumping node. The CTS method is widely used as with proper dynamic control technique of the MOSFETs to turn on/off entirely in the desired period ^[20].

Moreover, there was no voltage drop between the drain and source terminal. Hence, the MOSFET switch could shift the charge without suffering the constraint of the threshold voltage. The dynamic control circuit-controlled CTS to transfer the amounts from one stage to another without the threshold voltage drop ^[19]. However, the extra power dissipation of the parasitic capacitance caused the high-power indulgence in this scheme.

Yan et al. (2012) designed a CP circuit using an improved charge sharing method, which had six stages with six pumping capacitors at each pumping node. In this design, Yan et al. improved the charge pump circuit’s performance based on the CTS method. Moreover, a zero Vth

drop at every node. Furthermore, the charge transfer switches can turn on/off completely, and feedback current reduced. However, this design dissipated an enormous power with a small number of stages due to complex circuitry ^[21].

Wei et al. (2013) proposed an enhanced or NCP-2 CTS CP circuit to the shortest charge flow with improved voltage pumping gain. In this design, the diode-configured design limitations were managed using a proper clock scheme and the pumping capacitors’ sizing. Moreover, the strategy had the least parasitic capacitance effects. However, the system had low output voltage, higher power dissipation, and increase pumping efficiency ^[22].

In 2016, Zucchelli et al., proposed an inductor-based CP design scheme, fully integrated into DC/DC converter. Though the design was the modified version of the primary Dickson CP circuit, it provides enhanced performances due to small inductors’ involvement in the first stage of the charge transfer process as shown in Figure 4a,b. Therefore, the proposed design able to reduce power dissipation, rise time and output voltage ripple. Besides, this design was free from external components, making it compatible with CMOS technology ^[23].

Figure 4. (a) Schematic of the inductor-based CP circuit (b) first stage of the CP ^[23].

Rumberg et al., in 2017, came up with a new regulated CP circuit, which has designed based on floating-gate transistors. This type of structure is suitable for applications that required tunneling voltages to program floating-gate transistors. Due to its compact architectural design, the CP has leveraged variable frequency regulation and minimized short-circuit current to provide stable tunneling voltages. This design can reduce power dissipation. However, this circuit is not suitable for applications that needed standard CMOS transistors ^[24].

A high voltage generator based on the CP scheme has demonstrated by Abdi et al. in 2018, which features novel voltage regulation with a variable clock frequency. In this topology, an input voltage modulation has been added to a low-dropout regulator at the input stage to forward the input voltage to the next node. As a result, higher output voltage with stable voltage regulation has been achieved in this method. Moreover, thick-oxide transistors are employed to enhance the pumping efficiency and maintain the substrate/n-well voltage level during operation ^[25].

Rahman et al. proposed a modified charge transfer switch-based CP circuit in 2020 to be compatible with RFID tag EEPROM as shown in Figure 5. In this design, instead of diode-configuration, all NMOS switches in the charge transfer nodes. As a result, this topology could manage to reduce the substrate current and overall power dissipation. Additionally, in this design, the researchers can minimize the output ripple voltage and the chip layout area. This scheme has also integrated with a voltage regulator to produce a steady-boost voltage, the RFID tag memories requirement ^[26].

Figure 5. Schematic diagram of the CTS CP ^[26].

5. CP for Energy Harvesting

In 2008, Richelli et al. proposed a boosted CP design scheme suitable for energy harvesting. It has the feature of increasing output voltage from a very low supply voltage of about 150 mV. This scheme was designed using the new hybrid inductive and capacitive architecture. In particular, this method only consists of NMOS transistors, which were utilized as pass-transistors. Therefore, this scheme has a low threshold voltage compared to a PMOS-based CP circuit ^[27].

Shih and Otis et al. presented a modified four-phase CP circuit suitable for a fully integrated dc-dc converter for micropower energy harvesting. This modified CP can boost the voltage up to 3xVDD in free-running mode even if the input voltage automatically running down up to 270 mV. To do this autonomous voltage control, this modified CP did not use any external extraction. As a result, this adjusted CP ensured a regulated voltage supply at 1.4 V with only three µW power dissipation. However, this topology was unable to provide higher pumping efficiency with a higher chip area. Simultaneously, this mechanism is not compatible with many applications as the circuit modified to be compatible with DC–DC converter for micropower energy harvesting applications with stringent size constraints ^[28].

Recently, Peng et al. (2014) proposed a cross-coupled-based CP circuit following the Ker et al. design ^[29][30].The body biasing and backward charge pump scheme was introduced in this method, which could completely turn off/on the MOS transistors. As a result, voltage loss during switching reduced and the reverse charge sharing problem decreased. Moreover, low voltage operation was arisen due to the involvement of the sub-threshold organization. Nevertheless, two branch CP circuits designed by Peng et al. resolved all the boundaries of the Ker et al. CP circuit, where the pumping effectiveness was found 89% and 0.1 mS pumping speed was delivered. However, this designed CP required 320 mV for start-up, which was higher than other designs with high power dissipation due to its complex circuitry. Moreover, immense leakage current occurred due to unsuitable body biasing and controlling scheme.

Kim et al. (2015) proposed a CP circuit with dynamic body-biasing (DBB) to solve the limitations of high current transfer and high body leakages as shown in Figure 6. In this scheme, dead-time restrictions, conduction loss, and constraints were taking into concern during the design process regarding high voltage adaptation efficacy (VCE) and cut the power conversion efficiency (PCE) of ^[31].

In 2016, Mondal et al. proposed an inductor-less switching CP circuit suitable for solar energy harvesting. In this method, the charge transfer capability has improved and the charge sharing time to load. Moreover, in this scheme, a new single-clock tree-topology has been introduced to design the CP circuit, which has provided better charge transfer capability and sharing time. This proposed method has produced higher pumping efficiency for applications like the microscale energy harvesting system ^[32].

In 2019, Li et al. proposed a temperature-insensitive CP circuit, where the output voltage included a linear adjustment range. In this method, no bipolar-CMOS-DMOS (BCD) technology has been added to generate the output voltage higher than the n-well/substrate diode’s breakdown voltage, which has utilized triple-well NMOS. Besides, the pumping clock’s amplitude has been controlled continuously to produce a closed-loop regulation of voltage to make it insensitive to temperature changes. In a closed-loop control mechanism, the CP output has steady voltage regulation with a voltage deviation of only 1.1%. As a result, the proposed CP scheme has the compatibility of sensor accuracy for controlling micro gyroscopes. No external high voltage device must be integrated with the gyroscope measurement system ^[33].