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Bozsóki, I.; Géczy, A.; Illés, B. Thermomechanical Stress in Microelectronics Packaging Durability. Encyclopedia. Available online: (accessed on 22 June 2024).
Bozsóki I, Géczy A, Illés B. Thermomechanical Stress in Microelectronics Packaging Durability. Encyclopedia. Available at: Accessed June 22, 2024.
Bozsóki, István, Attila Géczy, Balázs Illés. "Thermomechanical Stress in Microelectronics Packaging Durability" Encyclopedia, (accessed June 22, 2024).
Bozsóki, I., Géczy, A., & Illés, B. (2023, August 24). Thermomechanical Stress in Microelectronics Packaging Durability. In Encyclopedia.
Bozsóki, István, et al. "Thermomechanical Stress in Microelectronics Packaging Durability." Encyclopedia. Web. 24 August, 2023.
Thermomechanical Stress in Microelectronics Packaging Durability

Reflow soldering is the main connection technology of surface mounting. Firstly, the solder in paste form is stencil-printed onto the solder pads of the applied substrate, and then surface mounted devices are placed onto the solder deposits. Finally, the whole assembly is heated over the melting temperature of the solder alloy, which melts and forms solder joints. Surface mounting technology needs a low defect rate which is determined by process parameters, material properties, and the printed circuit board design. Accompanying the experiment and measurement, the identification and elimination of root causes can be effectively improved with numerical modelling, which also grants details to such physical mechanisms that are not even conventionally measurable.

reflow soldering technology numerical modelling thermomechanical stress electronics packaging

1. Introduction

Thermomechanical stress, or simply thermal stress, is a well-known issue in microelectronics packaging durability. Temporal and spatial temperature gradient acting with different coefficients of thermal expansion in a composite structure result in different thermal expansions or contractions throughout the volume. Thermal stresses occur when any of these are constrained externally or internally. The board level analysis deals with the large-scale deformation of the assembly. At the component level, the mechanical stresses are investigated in the joints due to a CTE mismatch between the board and the component. Internal component stresses also studied were caused by thermal expansion accompanied by hygroscopic effects due to moisture content. Additionally, vapour pressure build-up in small cracks can lead to rapid crack growth during the reflow process. To reduce computational requirements, thermomechanical modelling approaches often omit transient stresses caused by non-uniform temperature distribution and prescribe the temperature uniformly in the structure following a standard reflow profile.

2. Analysis on Board Level

Warpage (out-of-plane deformation) along the boards was the focus of nonlinear programming in [1], during reflow soldering. The amorphous resin-based laminates underwent glass transition during heating, which decreased their elasticity and increased the thermal expansion coefficient. Two things affected the problem: the CTE mismatch between the prepreg layers and the copper and gravity are the root causes of warpage along the surface of PCBs. The theory of multi-layer laminated plates was used in the study to obtain the curvature at the lateral central point of the PCB. As concluded, additional dummy copper patterns and increased resin layer thickness can prevent the deformation rate at the cost of a larger weight and volume and a modification of the routing design. A similar warpage prediction study was presented in [2] based on the same multi-layer plate theory approach. Each layer was treated as a composite copper-epoxy material using the rule of mixtures with volume fractions, which is a common approximation method [3].
Gravity usually has a minor effect on thicker, smaller panels and a negligible effect on microelectronic components. However, the decreased bending stiffness of thin panels may cause reliability problems due to the additional mechanical stress during reflow. Large PCB arrays with 0.6 mm thickness, moving on a transition rail, were applied for deformation analysis due to gravitational forces in [4]. The prepreg and copper layers were modelled as linear elastic composite using volume fractions.
Warpage analysis of double-sided FR4 printed circuit boards and panelised PCB arrays were the focus of a study in [5] to determine the optimal router tab and array fixture design. A 3D FEM model was considered with large packages with a high pad count that exerted enough constraint after joint formation to affect the total warpage. All material models were linear elastic, including glass transition and orthotropic CTE. The model was validated via warpage measurement using the optical Shadow Moiré technique.
Another study [6] investigated a microwave SiP (system-in-package) module with ceramic substrates. QFN (quad flat no-lead) and QFP packages with other passive components were mounted on two levels of ceramic substrates interconnected with nickel-cobalt ferrous alloy (Kovar) columns. The module itself was mounted on FR4 PCB. Through 3D FEM simulation, warpage and stress variation were analysed during the reflow process. The viscoplastic Anand model was applied to the SAC solder balls. The results showed increasing warpage with the increase in maximum reached temperatures. The effective and residual stresses reached their maximum in the solder ball roots at the outermost diagonal corners.
Warpage was predicted at the board level with 3D FEM during FC reflow with an IR component in [7]. The layered PCB was populated with larger packages such as BGA using simplified models. Heat conduction was coupled with thermal stress calculation including glass transition. Convective and radiative boundary conditions were combined as heat transfer. The convective part was determined from Nusselt-type theory. The warpage increased with rising temperature and reached its maximum at the peak temperature. Besides ambient temperature and conveyor speed, the thickness of the board had the greatest impact on warpage percentage.
Warpage of PCB equipped with dual in-line memory module (DIMM) socket was experimentally studied and modelled in [8] at different thermal loads. The deformation caused by CTE difference between the socket and the PCB was calculated with 3D FEM using simplified linear elastic models, where the board and the socket were treated as composites. The elastic properties and CTE values of the materials were determined by in situ measurement and bending tests. An analytic solution was also proposed based on the beam bending theory.
Warpage and residual stresses induced during reflow soldering were investigated in an insulated gate bipolar transistor (IGBT) power module in [9]. These modules contain a thick copper base substrate, and thin direct bonded copper (DBC) plates are soldered onto it. DBC plates have a ceramic core, and the copper layer is patterned. The components are mounted and wire bonded onto the DBC plates, while the base substrate could be equipped with a massive heat sink from the other side. This structure ensures effective cooling for high-power current switching. These modules require a specialised reflow technique that uses a controlled hot surface to transfer heat to the substrate by direct contact. A vacuum is applied in the closed chamber above the liquidus temperature to eliminate solder voids. Predicting residual warpage is crucial to achieve excellent heat sink contact. A 3D FEM model was built including material plasticity and viscoplastic solder behaviour. The maximum stress (residual and effective) appeared in the ceramic plates due to the CTE mismatch compared to the copper substrate. It was found that deformation and stress can be safely reduced by decreasing the thickness of the ceramic plates or applying pre-warped copper substrates. This model was extended in [10] by changing to a coated AlSiC metal matrix composite substrate to decrease CTE difference. Temperature-dependent material properties and the effect of latent heat during phase change were also included.

3. Component Level Analysis

The diffusion of moisture in polymer materials in the case of improper storage may cause a “popcorn” cracking effect in the package. This means that there is a vapour pressure build-up during heat transfer in reflow ovens, causing a crack in the plastic body of the electronic component. Interfacial delamination is usually observable in such cases between the encapsulant material and lead frame in the package structure. Delamination originates from small voids or defects in material interfaces that arise during manufacture and are able to grow due to thermal stress. This complex phenomenon was modelled in [11]. A two-dimensional thin QFP package model with leadframe, epoxy moulding compound (EMC), and silicon die was investigated. A 2D FEM approach was applied in the study. The 0.2 mm long delamination interface was placed between the frame and EMC. Transient temperature, moisture concentration, and vapour pressure were the focus of the calculations. These parameters were then coupled to the stress field. The total energy release rate was determined based on the so-called “modified virtual crack closure” (MVCCT) technique. The results revealed that EMC material with a lower elastic modulus contained lower thermal stress. Similarly, lower CME and diffusion coefficient resulted in decreased hygrostress.
A similar 2D bi-material crack analysis in thin QFP packages was presented in [12], where a 0.5 mm crack was placed between the die pad and EMC. It was observed that the energy release rate and moisture concentration were found to be higher in packages with lower height. Furthermore, thermal strain due to CTE mismatch only contributed to 40–50% of the total energy release rate. This percentage increased with package thickness.
Bi-material crack analysis with moisture diffusion was further elaborated in [13] with 2D FEM model of a two-level stacked die package, including two silicon dies, moulding compound, die attach adhesive and epoxy substrate. The MVCCT was applied to analyse pre-made cracks at potential delamination interfaces at the die/die attach and die/moulding compound on both levels. The vapour pressure inside acted along the outward normal direction of the crack surfaces, proportionally to the local moisture content and the saturated water vapour pressure. According to the results, the energy release rates at the bottom die were larger than on the top level and increased with crack length. The growth trend became more significant at the peak temperature, indicating the significance of vapour pressure for larger cracks. Shear was found to be the dominant mode around the crack tip, originating from a CTE and CME mismatch.
Crack analysis was performed at the interface of the copper/copper-epoxy layers in the metal leads of a multi-layer ceramic capacitor using 3D FEM in [14]. Crack propagation from the initial micro voids was simulated as uneven thermal expansion between adjacent layers as tension load, which could lead to delamination. The theory was validated with a cross-section inspection of micro cracks and voids at the interface using a scanning electron microscope. The model was refined further by adding the effect of hygrostress due to moisture diffusion in [15].
Residual strain and warpage were investigated in plastic BGA packages during reflow and thermal cycling in [16]. A combination of Shadow Moiré measurement and 3D FEM simulation was applied, with a glass transition effect in the EMC material. It was shown that the residual strain increased with the glass transition temperature. The approach was improved further in [17] with temperature dependent CTE and viscoplastic SAC solder ball material. The heating was modelled with convective boundary conditions using prescribed heat transfer coefficients and ambient temperatures to emulate the reflow profile. The maximum convex warpage appeared during the first section of cooling, and its magnitude decreased for thicker PCBs.
Thermal stresses and warpage in the ball array of a BGA were analysed during cooling in [18][19]. A slow cooling rate may result in a large grain size and excessive intermetallic growth in solder joints, causing weak fatigue resistance. On the other hand, a fast cooling rate may lead to a high level of thermal stress causing internal cracking in the joint or bonding pad delamination. Influent gas flow (nitrogen) and the resulting coefficient of heat transfer were calculated on a coarsely detailed FR4 PCBA with RANS, applying a 3D FVM approach. The calculated board level thermal response was transferred to a more detailed sub-model to determine thermal stresses in the SAC solder joints with FEM. It was found that the inlet velocity affected the process the most. This was followed by the cooling temperature, conveyor speed, and PCB density. The maximal effective stress appeared at the roots of the bumps, where the board and the package substrate acted as constraints with different CTE values.
Thermal stresses and warpage in a mounted flip-chip were modelled in [20] with 3D FEM due to a CTE difference between the chip and the FR4 board. Only the cooling section was simulated considering the high temperature state before solidification as stress free. A constant heat transfer coefficient was used, and the result was convex warpage, because the FR4 contracted more than the silicon chip.
Internal stresses in a QFP component were investigated during reflow process in [21]. The most critical material interfaces in a QFP package are between the lead frame and the die attach, as well as between the silicon die and EMC. A 3D FEM approach was applied to a linear elastic model. The focus was on the interfaces between materials with detailed structural definition. It was shown that the maximum effective stress appeared in the interface between the die attach and the copper pad. This was the case in both constrained (joined with solder) and free configurations, although it was nearly tripled in the constrained one.


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