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Li, H. DEC 3000 AXP. Encyclopedia. Available online: (accessed on 11 December 2023).
Li H. DEC 3000 AXP. Encyclopedia. Available at: Accessed December 11, 2023.
Li, Handwiki. "DEC 3000 AXP" Encyclopedia, (accessed December 11, 2023).
Li, H.(2022, November 30). DEC 3000 AXP. In Encyclopedia.
Li, Handwiki. "DEC 3000 AXP." Encyclopedia. Web. 30 November, 2022.
DEC 3000 AXP

DEC 3000 AXP was the name given to a series of computer workstations and servers, produced from 1992 to around 1995 by Digital Equipment Corporation. The DEC 3000 AXP series formed part of the first generation of computer systems based on the 64-bit Alpha AXP architecture. Supported operating systems for the DEC 3000 AXP series were DEC OSF/1 AXP (later renamed Digital UNIX) and OpenVMS AXP (later renamed OpenVMS). All DEC 3000 AXP models used the DECchip 21064 (EV4) or DECchip 21064A (EV45) processor and inherited various features from the earlier MIPS architecture-based DECstation models, such as the TURBOchannel bus and the I/O subsystem. The DEC 3000 AXP series was superseded in late 1994, with workstation models replaced by the AlphaStation line and server models replaced by the AlphaServer line.

computer workstations alphaserver servers

1. Models

There were three DEC 3000 model families, codenamed Pelican, Sandpiper, and Flamingo. Within Digital, this led to the DEC 3000 series being affectionately referred to as "the seabirds".

Model Codename CPU CPU MHz B-cache (L2) Chassis Introduced Withdrawn
Model 300 Pelican EV4 150 256 KB Desktop ?
Model 300L Pelica EV4 100 256 KB Desktop 1994-03-25
Model 300X Pelican+ EV4 175 256 KB Desktop 1994-02-08 1995-10-02
Model 300LX Pelica+ EV4 125 256 KB Desktop 1994-02-08 1995-06-23
Model 400 Sandpiper EV4 133 512 KB Desktop ?
Model 500 Flamingo EV4 150 512 KB Pedestal ?
Model 500X Hot Pink EV4 200 512 KB Pedestal ?
Model 600 Sandpiper+ EV4 175 2 MB Desktop 1993-10-13 1995-10-02
Model 700 Sandpiper45 EV45 225 2 MB Desktop 1995-10-02
Model 800 Flamingo II EV4 200 2 MB Pedestal 1993-10-13 1994-02-12
Model 900 Flamingo 45 EV45 275 2 MB Pedestal 1995-10-02

Note: Server configurations of the Model 400/500/600/700/800/900 systems were suffixed with "S".

2. Description

The logic in Flamingo- and Sandpiper-based systems are contained on two modules (printed circuit boards), the CPU module and the I/O module, with the CPU module being the largest board. The two modules are connected via a 210-pin connector. The logic in Pelican-based systems are contained the CPU module and system module. The CPU module is a daughterboard that plugs into the system module and contains the CPU and the B-cache (L2 cache).

The architecture of the Flamingo- and Sandpiper-based systems is based around a crossbar switch implemented by an ADDR (Address) ASIC, four SLICE (data slice) ASICs and a TC (TURBOchannel) ASIC. These ASICs connect the various different width buses used in the system, allowing data to be transferred to the different subsystems. PALs were used to implement the control logic. The cache, memory and TURBOchannel controllers, as well as other control logic, is entirely implemented by PALs. Pelican-based systems have an entirely different architecture from the other systems, similar to that of late-model Personal DECstations that they are based on, with a traditional workstation architecture with buses and buffers.

2.1. Memory

The Sandpiper and Flamingo used proprietary 100-pin, 40-bit (32 bits plus 8 bits ECC) Fast Page Mode SIMMs with capacities of 2 MB, 4 MB, 8 MB, 16 MB or 32 MB.[1] These were eight-way interleaved, providing a 256-bit-wide bus to memory. The Sandpiper had two such eight-SIMM banks, for up to 512 MB total system RAM, while the Flamingo had four banks and supported up to 1 GB. In comparison, the Pelican was a budget architecture utilising eight standard 72-pin Fast Page Mode SIMMs that were protected with longword parity instead of ECC, with capacities of 8 MB or 32 MB, for a total of up to 256 MB RAM. These were two-way interleaved, for a 64-bit-wide bus to memory.

2.2. Expansion Slots

The DEC 3000 AXP series uses the 32-bit TURBOchannel bus running at various speeds, 12.5 MHz in the 300 models, 22.5 MHz in the 400 models and 25 MHz in models 500 to 900. The TURBOchannel bus is provided by an ASIC, which connected it to the SLICE data path ASICs. The number to expansion slots also varied, the 300 models had two slots, except for the 300L, which had none. Models 400, 600 and 700 had three slots, the model 500X featured five, while models 500, 800 and 900 featured six.

2.3. Graphics

The Model 300 Series and the Model 500, 500S and 500X feature integrated graphics provided by the CXTurbo subsystem, which resides on the system module. This subsystem is essentially an onboard HX TURBOchannel option module. The subsystem features a SFB (smart frame buffer) ASIC, a Brooktree Bt459 RAMDAC, 2 MB of VRAM and in the Model 500, 500S and 500X, a 256 KB flash ROM that holds part of the system firmware. The CXTurbo subsystem can reach resolutions of 1280 × 1024 at 72 Hz in the 300, 300X and 300LX models, 1024 × 768 at 72 Hz in the Model 300L and 1280 × 1024 at 66 Hz or 72 Hz in the Model 500, 500S and 500X.

Because of the DEC 3000 AXP's similarity with Digital's previous RISC workstation line, the DECstation, the same TURBOchannel graphics options, which consisted of framebuffers, 2D and 3D accelerated graphics, were carried over the DEC 3000 AXP. Like the DECstation, up to three (the actual number may be less, depending on the number of TURBOchannel option slots the system features) framebuffers of the same model can be installed in a single system to support multiscreen configurations.

Despite using the same graphics options as the DECstation at introduction, later options for the DEC 3000 AXP were designed exclusively for the platform. These options were Digital's ZLX-E1/E2/E3, ZLX-L1/L2 and ZLX-M1/M2 series of PixelVision architecture-based 2D/3D accelerated graphics and Kubota's high-end 3D accelerated graphics subsystem, the Denali. The Denali is an external enclosure that contains up to six geometry engines and multiple memory modules. It was capable of advanced (for the time) 3D graphics, such as interactive volume rendering. It connects to the DEC 3000 AXP via a cable and a TURBOchannel interface module.

2.4. I/O Subsystem

The I/O subsystem provides the DEC 3000 AXP with Ethernet, ISDN and audio capability, four serial lines, and a real time clock. The I/O subsystem is interfaced to TURBOchannel by the IOCTL ASIC, which also implements two 8-bit buses, known as IOBUS HI and IOBUS LO, to which the I/O devices connect to. These two 8-bit buses can be combined to serve as one 16-bit bus to provide an I/O device with more bandwidth. Ethernet is provided by an AMD Am7990 LANCE (Local Area Network Controller for Ethernet), an AMD Am7992 SIA (Serial Interface Adapter) that implements the 10BASE-T or AUI Ethernet interface, and an ESAR (Ethernet Station Address ROM) that stores the MAC address. The Am7990 is the only I/O device in the subsystem to have a 16-bit interface to the IOCTL ASIC. ISDN and telephone-quality audio is provided by an AMD Am79C30A DSC (Digital Subscriber Controller). The four serial lines are provided by two Zilog Z85C30 SCC (Serial Communications Controller) dual UARTs, and the real time clock is a Dallas Semiconductor DS1287A.

2.5. SCSI Interface

The DEC 3000 AXP used a TCDS (TURBOchannel Dual SCSI) ASIC to provide an interface between the SCSI controllers and the TURBOchannel bus. Early systems used one (Model 300s) or two (Model 400 and 500) NCR 53C94 SCSI controllers, which provided one or two 5 MB/s[2] 8-bit single ended SCSI buses. Later and higher end systems such as the Model 600, 700, 800 and 900 also feature two SCSI controllers, but used the NCR 53CF94-2 instead, which provided faster 10 MB/s 8-bit single ended SCSI buses.


  1. When applied to computer memory (RAM or cache) the quantities KB, MB and GB are defined as: 1 KB = 1024 B 1 MB = 1024 KB 1 GB = 1024 MB, consistent with the JEDEC memory standard.
  2. When applied to parallel data transfer, the unit MB is defined as 1 MB = 1,000,000 B, so that 1 MB/s = 1,000,000 bytes per second.
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