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| Version | Summary | Created by | Modification | Content Size | Created at | Operation |
|---|---|---|---|---|---|---|
| 1 | Dean Liu | -- | 2589 | 2022-11-18 01:37:28 |
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The XCore Architecture is a 32-bit RISC microprocessor architecture designed by XMOS. The architecture is designed to be used in multi-core processors for embedded systems. Each XCore executes up to eight concurrent threads, each thread having its own register set, and the architecture directly supports inter-thread and inter-core communication and various forms of thread scheduling. Two versions of the XCore architecture exist: the XS1 architecture and the XS2 architecture. Processors with the XS1 architecture include the XCore XS1-G4 and XCore XS1-L1. Processors with the XS2 architecture include xCORE-200. The architecture encodes instructions compactly, using 16 bits for frequently used instructions (with up to three operands) and 32 bits for less frequently used instructions (with up to 6 operands). Almost all instructions execute in a single cycle, and the architecture is event-driven in order to decouple the timings that a program needs to make from the execution speed of the program. A program will normally perform its computations and then wait for an event (e.g. a message, time, or external I/O event) before continuing.
References
- "xCORE-200: The XMOS XS2 Architecture" (PDF). XMOS. 2016-12-21. https://www.xmos.com/published/xs2-isa-specification.
- "XMOS announces world’s lowest cost, most flexible AI processor". XMOS. https://www.xmos.com/xmos-announces-worlds-lowest-cost-most-flexible-ai-processor.
- "XMOS adapts Xcore into AIoT ‘crossover processor’". EE Times. https://www.eetimes.com/xmos-adapts-xcore-into-aiot-crossover-processor.
- "Insightful analysis of xcore.ai from The Linley Group". The Linley Group. https://www.xmos.com/insightful-analysis-of-xcore-ai.
- The architecture manual documents bit 5 as the "most significant bit", but fails to mention the non-binary base; some XS-1 disassembler source code makes it clear. In the definition of parse-inssn-r2, the 1 #split 1b - swap 5 * + portion splits the 6-bit register field into a 5-bit and a 1-bit part, subtracts 27 (hex 1b) from the high part, multiplies the low part by 5, and adds them. http://git.infradead.org/users/segher/dis-xs1.git/blob/HEAD:/dis-xs1.fs
- David May. "XMOS XS1 Architecture" (PDF). XMOS. https://www.xmos.com/published/xmos-xs1-architecture. (Free registration required)
- Jurij Šilc; Borut Robič; Theo Ungerer (1999). Processor Architecture. Springer. ISBN 3-540-64798-8. https://archive.org/details/processorarchite0000silc.
