1. ABM (Advanced Bit Manipulation)

ABM is only implemented as a single instruction set by AMD; all AMD processors support both instructions or neither. Intel considers POPCNT as part of SSE4.2, and LZCNT as part of BMI1. POPCNT has a separate CPUID flag; however, Intel uses AMD's ABM flag to indicate LZCNT support (since LZCNT completes the ABM).^[1]

LZCNT is related to the Bit Scan Reverse (BSR) instruction, but sets the ZF (if the result is zero) and CF (if the source is zero) flags rather than setting the ZF (if the source is zero). Also, it produces a defined result (the source operand size in bits) if the source operand is zero. For a non-zero argument, sum of LZCNT and BSR results is argument bit width minus 1 (for example, if 32-bit argument is 0x000f0000, LZCNT gives 12, and BSR gives 19).

The encoding of LZCNT is such that if ABM is not supported, then the BSR instruction is executed instead.^[2]:227

2. BMI1 (Bit Manipulation Instruction Set 1)

The instructions below are those enabled by the BMI bit in CPUID. Intel officially considers LZCNT as part of BMI, but advertises LZCNT support using the ABM CPUID feature flag.^[1] BMI1 is available in AMD's Jaguar,^[3] Piledriver^[4] and newer processors, and in Intel's Haswell^[5] and newer processors.

TZCNT is almost identical to the Bit Scan Forward (BSF) instruction, but sets the ZF (if the result is zero) and CF (if the source is zero) flags rather than setting the ZF (if the source is zero). For a non-zero argument, the result of TZCNT and BSF is equal.

As with LZCNT, the encoding of TZCNT is such that if BMI1 is not supported, then the BSF instruction is executed instead.^[2]:352

3. BMI2 (Bit Manipulation Instruction Set 2)

Intel introduced BMI2 together with BMI1 in its line of Haswell processors. Only AMD has produced processors supporting BMI1 without BMI2; BMI2 is supported by AMDs Excavator architecture and newer.^[8]

3.1. Parallel Bit Deposit and Extract

The PDEP and PEXT instructions are new generalized bit-level compress and expand instructions. They take two inputs; one is a source, and the other is a selector. The selector is a bitmap selecting the bits that are to be packed or unpacked. PEXT copies selected bits from the source to contiguous low-order bits of the destination; higher-order destination bits are cleared. PDEP does the opposite for the selected bits: contiguous low-order bits are copied to selected bits of the destination; other destination bits are cleared. This can be used to extract any bitfield of the input, and even do a lot of bit-level shuffling that previously would have been expensive. While what these instructions do is similar to bit level gather-scatter SIMD instructions, PDEP and PEXT instructions (like the rest of the BMI instruction sets) operate on general-purpose registers.^[9]

The instructions are available in 32-bit and 64-bit versions. An example using arbitrary source and selector in 32-bit mode is:

AMD processors before Zen 3^[10] that implement PDEP and PEXT do so in microcode, with a latency of 18 cycles^[11] rather than a single cycle. As a result, if the mask is known, it is often faster to use other instructions on AMD.

4. TBM (Trailing Bit Manipulation)

TBM consists of instructions complementary to the instruction set started by BMI1; their complementary nature means they do not necessarily need to be used directly but can be generated by an optimizing compiler when supported. AMD introduced TBM together with BMI1 in its Piledriver^[4] line of processors; later AMD Jaguar and Zen-based processors do not support TBM.^[3] No Intel processors (at least through Coffee Lake) support TBM.

5. Supporting CPUs

• Intel
  • Intel Nehalem processors and newer (like Sandy Bridge, Ivy Bridge) (POPCNT supported)
  • Intel Silvermont processors (POPCNT supported)
  • Intel Haswell processors and newer (like Skylake, Broadwell) (ABM, BMI1 and BMI2 supported)^[5]
• AMD
  • K10-based processors (ABM supported)
  • "Cat" low-power processors
    • Bobcat-based processors (ABM supported)^[13]
    • Jaguar-based processors and newer (ABM and BMI1 supported)^[3]
    • Puma-based processors and newer (ABM and BMI1 supported)^[3]
  • "Heavy Equipment" processors
    • Bulldozer-based processors (ABM supported)
    • Piledriver-based processors (ABM, BMI1 and TBM supported)^[14]
    • Steamroller-based processors (ABM, BMI1 and TBM supported)
    • Excavator-based processors and newer (ABM, BMI1, BMI2 and TBM supported; microcoded PEXT and PDEP)^[8]
  • Zen-based, Zen+-based, and processors (ABM, BMI1 and BMI2 supported; microcoded PEXT and PDEP)
  • Zen 3 processors and newer (ABM, BMI1 and BMI2 supported; full hardware implementation)

Note that instruction extension support means the processor is capable of executing the supported instructions for software compatibility purposes. The processor might not perform well doing so. For example, Excavator through Zen 2 processors implement PEXT and PDEP instructions using microcode resulting in the instructions executing significantly slower than the same behaviour recreated using other instructions.^[15] (A software method called "zp7" is, in fact, faster on these machines.)^[16] For optimum performance it is recommended that compiler developers choose to use individual instructions in the extensions based on architecture specific performance profiles rather than on extension availability.