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FPGA in Decimal Arithmetic
Decimal operations are executed with slow software-based decimal arithmetic functions. For the fast execution of decimal operations, dedicated hardware units have been proposed and designed in FPGA. Decimal addition and multiplication is found in most decimal-based applications and so its design is very important for fast execution. This entry describes recent solutions for decimal multiplication and addition in FPGA.
Financial and commercial applications like accounting, banking, tax calculation, insurance and currency conversion require a large amount of data computing. Therefore, they are typically executed in high-performance computing platforms. These applications run over large databases of numbers which, in many cases, are represented in decimal format . The last revision of the IEEE standard for floating-point arithmetic  includes specific definitions and rules for decimal operations and three different formats: decimal 32, decimal 64 and decimal 128, with 7, 16 and 34 coefficient digits.
Most general-purpose processors only have binary arithmetic units. So, the fastest solution to run decimal operations would be to convert decimal numbers to binary before being processed and then convert the result to decimal. The problem is that not all decimal numbers can be represented exactly as binary numbers with a finite number of bits. So, to avoid errors created from binary calculation that could lead to unwanted result deviations, arithmetic operations must be done directly over decimal numbers.
Executing decimal operations with binary arithmetic hardware without converting data to binary requires software algorithms for decimal arithmetic. Software-based decimal arithmetic is very slow compared to binary arithmetic implemented in hardware. However, the fast increase of commercial and financial transactions requires fast decimal arithmetic computing to meet real-time requirements and exact computations. Decimal addition and multiplication are fundamental arithmetic operations used in many applications. Therefore, fast decimal multipliers are important to obtain fast decimal-based applications.
FPGAs (Field Programmable Gate Array) are a good alternative for the execution of decimal arithmetic with dedicated hardware modules.
2. Decimal Addition in FPGAw+z+6≤15
adders followed by correction stages were also implemented in 6-input LUT FPGAs .
3. Decimal Multiplication in FPGA
fast execution, parallel decimal multiplication consists of partial product generation for each multiplier digit followed by partial product addition. Partial product generation of a N×N multiplication can be implemented with N×N small digit by digit multipliers or N digit by multiplicand multipliers. A digit by digit multiplier can be implemented with logic or with look-up tables ), for fast and compact design. However, given the quadratic number of digit by digit multipliers necessary to implement a multiplication, these solutions are viable only for small operand sizes. The proposal in  considered recoding of operands to simplify digit by digit multiplication for partial product generation. However, the performance and area of the decimal multiplier based on digit by digit multiplication is still worst than a multiplier with a partial product for each multiplier digit.
The entry is from 10.3390/a14070198
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