The manufacture and construction layout of the cell is fabricated on the front side with a boron emitter and backside with a passivating connecting layer, as well as with equal side fingers applied through a screen-printed approach to build a bi-facial solar cell. Small quantities of oxygen are needed for doping the wafers by phosphorus, including a resistivity value of about 0.4 Ω cm to 1.1 Ω cm. By utilizing a potassium hydroxide (KOH) solution, the wafers are textured on both sides with the pyramids of the irregular pattern. Following the RCA cleaning process and applying the boron tribromide (BBr₃) gas, the boron emitter is produced in the furnace of boron diffusion. The backside boron diffusion is removed by applying the etching process on one side by utilizing the solution of nitric acid and hydrofluoric acid (HF/HNO₃). The thermal oxidation is performed before the Boron Silicate Glass (BSG) removal. A tunneling SiO_x layer is thermally established when wafers are cleaned with chemicals. For the PECVD, silane (SiH₄), hydrogen (H₂), and phosphine (PH₃) are used as precursor gas sources for phosphorus-doped amorphous silicon (n-a-Si:H) growth. After annealing at 900 °C in a N₂ environment for the dwell time of 30 min, n-a-Si:H is transformed into phosphorus-doped poly-Si layers (n⁺-poly-Si), which comprised n⁺-poly-Si on the c-Si/SiO_x structure (n⁺-poly-Si/SiO_x/c-Si contact). The boron emitter that passivated through the layer of the dielectric film, consequently, further RCA cleaning is carried out, specifically similar work out as anti-reflection layer of coating. The backside SiO_x/n⁺-polysilicon coating is enclosed with PECVD SiN_x:H. On both surfaces, an “H-metal contact” with Ag busbars is applied through screen printing for metallization. Subsequently, a quick-firing method with a maximum temperature of approximately 760 °C is applied [33]. Following the fabrication of the TOPCon solar cell, further essential solar cell characterizations such as IV curves and further considerations remain premeditated with a relevant 1-sun (1000 W/m²) IV analyzer.

In the past few years, the c-Si solar cell has been meticulously studied. When the metal is completely contiguous with the silicon wafer, the consequence is extreme electrical loss owing to the presence of electrons recombination in the solar cell because of the higher absorption of electrons at the junction area. In the preceding model, around two methods remained to decrease the metal carrier recombination accurately within the interaction with the silicon wafer: (1) through retaining a minor layer of the passivated silicon film, and (2) by diminishing the interaction capability and with the help of effortlessly developed doping to separate the metal from silicon wafer [56,57,58].

The main advantage of the foregoing methodologies is a passivated emitter and rear cell (PERC), that is after a conventional PN junction construction, with indigenous doping only in the contact area of the emitter. Currently, its efficiency at the current condition can achieve maximum of 25.0% [59]. The next approach for the previous method is heterojunction with intrinsic thin-layer (HIT) solar cells, as described by the Panasonic company. Such solar cells currently depict an efficiency of these cells around 26.7% [59,60].

The TOPCon solar cell can moreover seem as consequential after the typical PN junction structure, associated with the improvements of the two techniques described before. During the past few decades, owing to commendable passivation, the TOPCon solar cell turned out to build for the majority of research across technical organizations. The solar cell having n-type wafer with complete specific selective back contact charge carrier and double-sided interconnected solar cell, including a maximum efficiency, was reported to have approximately 26.7% efficiency by Fraunhofer [59,60]. The maximum efficiency is owing to the fact wherein the n-type wafer provides a superior impurity that permitted improvement, and the flaws in the faces are passivated entirely. The majority of the materials being revealed that substrate resistivity between 1 and 10 Ω cm utilized for the TOPCon solar cell are able to achieve an efficiency higher than 25% [58]. For the improvement in the efficiency of solar cells and to retain a process that should be capable of continue to enhance, the selective contact charge carrier comes to developed in the proposed TOPCon solar cell. Unlike conventional silicon type of solar cells, TOPCon achieves the following important characteristics and key features [61,62]:

• The ultimate oxides layer at the nano-scale assured the hanging bond that is found at a single crystal surface, consequently improving the conversion efficiency;
• Depending on the range of substrate conductivity, the oxide layer at nano-scale level permits instant transport of the holes or electrons;
• Owing to the importance of the high possibility of densely doped polysilicon conductivity, the junction resistivity can be reduced, and the output current might become better.

The elementary design of the TOPCon solar cell structure is shown in Figure 1, mainly generated with a PN junction on the substrate of an n-type material [58,63]. The cell is passivated with a nano-scale layer of aluminum oxide (Al₂O₃) on the p-type material surface and includes an extremely thin coating of approximately 2 nm with a Silicon dioxide (SiO₂) tunneling layer and a highly doped polysilicon layer on the n-type material surface [64]. The surface passivation by the tunneling oxide layer is the most important attribute of the TOPCon solar cell, along with the selective contact to accomplish the exceptionally minimum recombination level after the highly doped layer of polysilicon. To permit many of the carriers to the tunnel, the tunneling layer of SiO₂ requires to be sufficiently fine to transport though. Similarly, their field effect must be able to prevent transmission of the minority carriers [65]. Properties of the passivation layer for the highly doped level of the polysilicon layer are varied by adjusting the concentration rate of hydrogen through physical vapor deposition (PVD). For instance, atomic layer deposition (ALD) sputtering, or chemical vapor deposition (CVD) such as plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD). Because of the enormous amount of hydrogen atoms in the highly doped polysilicon layer, it shows reasonable properties of passivation [66].

The trends of pinhole and tunneling are two unique forms of charge carrier transportation configurations that arise at interfaces of poly-Si/SiO_x/c-Si. Figure 2 demonstrates the situation of carrier transport that happens at the layer of SiO_x. Such structures take place according to the width of SiO_x thickness and annealing temperatures.

Feldmann et al. explored SiO_x tunneling layer experiences maintaining thicknesses of not more than 1.5 nm [52]. The main charge carrier conduction was investigated through the tunneling layer by SiO_x. Recent research was enhanced by the simulation modeling performed by Steinkemper et al. 

Likewise, the process of the pinhole occurs with a thickness of more than 2 nm of SiO_x that is significantly annealed at higher temperatures of approximately 1000 to 1050 °C. The resulting prevalent technique for such kinds of contacts remained precisely controlled over pinholes within the c-Si layer along with poly-Si which were developed through annealing at a high temperature in the SiO_x layer [67,68]. Although the oxide layer thickness is conflicting in different progress methods [46], the trend of tunneling takes place in oxides from not more than 2 nm because it is incredibly challenging to tunnel the charge carriers by concentrated oxide coatings [69]. The findings after the performance simulation by Zhang et al. upon nano-scaled tunnel oxide (SiO_x, less than 1.5 nm) layer show very high features of tunneling and efficiency by preventing the carrier transport by pinhole [70]. However, a relatively dense SiO_x layer (more than 1.1 nm) exhibited minimum fill factor (FF), and efficiency through larger resistivity does not permit any carrier transportation beyond the pinholes.

The transportation of the minimum carrier over the pinholes improves the FF and minimizes the resistance, consequently enhancing the PCE. Wietler et al. analyzed restrain carrier transport by pinholes through selective etching surface of oxide layer on the junction of the POLO structure [53]. A greater density of pinhole concentration would generate maximum saturation current density and negligible contact resistivity (ρ_c) of approximately 10 mΩ cm². The thickness of the SiO_x layer entails the electrical characteristics of the TOPCon solar cell. The current investigation by Wang et al. described three distinct oxide layer thicknesses as 1.25, 1.42, and 1.55 nm, which exhibited inconsistency in efficiency and other electrical parameters of TOPCon solar cells [71]. At 1.55 nm oxide layer thickness, good quality and regular surface are obtained after the etching, and it holds a minimum J₀ value of approximately 18 fA/cm², with FF = 81.09% and V_oc = 687 mV. However, the nano-scaled oxide layer at the thickness of 1.25 and 1.42 nm shows insufficiencies that are ascribed to the passivation failure at the nano-scaled oxide layer along with the pinhole’s progression. Adjusting the accurate temperature for annealing, this one decreases the development of pinhole concentration [72]. The exceptional productivity preceding technology of the TOPCon solar cell continues to determine the specific thickness of the nano-scaled tunnel oxide layer and efficient pinhole concentration for the enhancement in efficiency. The TOPCon solar cell structure holds the lowest value of saturation current density (J₀) for equally p-type and n-type poly-Si around (J₀ = 2 to 8 fA/cm²). Previously, the doping of poly-Si through phosphorous had better qualities than the poly-Si with boron-doping [73]. However, through research, it became obvious that the n-TOPCon has a good property for the layer of passivation between c-Si wafers of p-type and n-type, demonstrating an excellent value of V_oc in comparison with the p-TOPCon [41].

It is not only tunneling that moves the charge through the pinholes; both the transportation through the pinholes and the tunneling occurs together. For example, excessively thick oxide might provide a high tunneling barrier, although charge transfer through pinholes is possible. However, tunneling is more prevalent in the case of dense nano-scaled oxide. The type of conductivity is the factor that matters most. Due to the band-bending orientation, it was shown that p-Si/SiOx/p+-Si can only transport holes and not electrons, and vice versa.