Tunneling and Blocking Oxides on Memory Cells

Version	Summary	Created by	Modification	Content Size	Created at	Operation
1		Dencho Spassov	--	3201	2023-09-05 11:52:58	\|
2	layout	Camila Xu	-1 word(s)	3200	2023-10-20 10:05:56	\|

This entry is adapted from the peer-reviewed paper 10.3390/nano13172456

Flash memory is an electronic, non-volatile information storage device that can be electrically erased and reprogrammed. Ideally, the information stored in such a device should be preserved for long when the power is switched off. There are two flash memories designs at present: floating gate and charge trapping. Both of them work by storage of electrical charges in the space above the channel of the MOSFET. The charge storage volume of the flash cell, either poly-Si floating gate or charge trapping dielectric/dielectric stack is confined between blocking and tunnel oxides for electrical insulation from the gate electrode and Si substrate. Blocking and tunnelling oxides are important parts of the flash memory cells, as they affect retention, endurance and program/erase speed performance.

charge trapping flash memory HfO2/Al2O3 stacks non-volatile memory atomic layer deposition (ALD)

1. Introduction

Flash memory is an electronic, non-volatile information storage device that can be electrically erased and reprogrammed. Ideally, the information stored in such a device should be preserved for long when the power is switched off. Flash memories are the primary means to realize low-cost and high-density data storage needed for all major end-user gadgets (smartphones, PCs, USBs, medical devices, electronic games, etc.). The ever-widening field of possible applications made flash memories the fastest-growing product in the history of the semiconductor market (Figure 1).

Figure 1. Flash memory market trends. Data from 1990 to 2006 by ^[1], from 2007 to 2012 from ^[2] and from 2013 to 2021 by ^[3].

For a long time, the dominant flash NVM technology was the floating gate (FG) memory cell ^[4]^[5]. The idea for the FG memory cell was proposed by Kahng and S.M. Sze in 1967 ^[6]. Its operation principle is based on charge storage in an electrically isolated floating poly-Si gate. This floating gate is stacked in between a thin tunnelling (6–7 nm) oxide and interpoly dielectric (10–13 nm) (Figure 2a). By applying a pulse to the control gate, the electrons are injected from the transistor’s channel to the floating gate and stored there until the pulse with opposite polarity forces them out of the floating gate. The presence/absence of electrons on the floating gate changes the threshold voltage, thus forming the memory window. The charges stored in the electrically isolated floating gate remain there for a long time, thus defining the non-volatile character of memory. The increasing demands for larger volumes of stored data cause an aggressive down-scaling of FG cell sizes. As a consequence, some of the intrinsic limitations of floating gate technology have been reached, e.g.,: (i) the thickness scaling of tunnel oxide and inter-poly dielectric layer compromises the reliability; (ii) a significant decrease in the number of electrons accumulated in FG as its dimensions decrease; (iii) it is difficult to maintain a high coefficient of capacitive coupling of the control gate to the floating gate; (iv) the parasitic capacitance between adjacent cells leading to data interference becomes important, etc.

Figure 2. Schematic comparison between basic MOS transistor structures in floating gate (a) and charge trapping memory devices (b).

Therefore, several new approaches to achieve a non-volatile programmable memory effect have been proposed: ferroelectric field effect transistor, resistive switching memory, nanoelectromechanical memory, spin-transfer torque memory, phase change memory, etc. All these new memory concepts are classified as emerging memories and rely on distinctly different physical phenomena and principles than currently used. For most of them, the architecture of the device/memory cell, as well as the materials, are quite different than those already adopted in the microelectronic industry, and there are a lot of problems with making them compatible with the current technology, which eventually requires abandoning the CMOS paradigm. A comprehensive review of the operation principles, advantages, and shortcomings of these new NVM concepts can be found in ^[7]. Still, none of the above-mentioned innovative devices and technologies has been identified as the most prospective and clear winner to replace CMOS–based memory cells.

In summary, new computing and data storage paradigms (like neuromorphic or quantum), novel architectures and devices using charges or, in the longer term, alternative state variables (e.g., spin, magnon, phonon, photon, etc.) are required to scale information processing technology substantially beyond that attainable by the ultimately scaled CMOS ^[8]. While developing these new technological approaches and paving the way for their adoption by the industry, there are still innovations within the current technology paradigm, which have been implemented to increase the bit density of NVM. These are, for example, an increase in the number of up to 4 bits per memory cell and replacing the floating gate cell with a charge trap cell ^[9].

Charge trapping flash (CTF) NVMs (Figure 2b) are a promising alternative to the conventional floating gate technology because they involve a more simplified process flow accompanied by better operation characteristics, e.g., improved retention and endurance, lower power consumption, higher program/erase (P/E) speed ^[10]^[11]^[12]. The charge-trapping memory is proposed by H. A. R. Wegner et al. ^[13]. CTF operation is similar to the floating gate cell, but the charge in CTF is stored in spatially discrete traps in the band-gap of the dielectric layer instead of the conducting floating poly-Si gate. This mode of charge storage offers a significant advantage over FG because the discharge of the whole stored charge is prevented in the case of an isolated defect in the tunnel oxide (hence the leakage path), and only charges stored in traps adjacent to the leakage path may be lost. The architecture of CT memory is very similar to MOSFET. Hence, it is compatible with CMOS technology. The importance of CTF became undeniable when flash memories switched from scaling horizontally to stacking vertically. Flash products have already overcome the 2D limitations by aggressively implementing 3D memory cell structures—72–96 layers of NAND memory cells have already been demonstrated ^[8]. The use of CT-NVM is also favourable in Vertical-NAND flash memory technology as it is more easily stacked vertically ^[14].

The most important part of the CT memory is the charge-trapping stack (Figure 2b). It consists of three layers—a charge trapping layer (CTL), where the charges are stored in traps. CTL is stacked in between the tunnelling and blocking oxides. Tunnelling oxide (TO) is used for more efficient injection of charges from the substrate/FET channel to CTL to prevent the trapped charges from back tunnelling to the substrate and to improve the retention characteristics. On the other hand, to form a potential barrier against the undesirable movement of electrical charges (holes/electrons) to and from the gate electrode, a thick enough blocking oxide (BO) should be introduced, and its band offset with the CTL should be of sufficient height. Therefore, the use of SiO₂ with its band-gap Eg of about 9.1 eV both as a blocking and a tunnelling oxide is a natural choice.

Moreover, recent technology allows SiO₂ to be grown with very low densities of defects and traps, which may participate in the process of charge loss. In the current CTFs, Si₃N₄ is used as a CTL because Si₃N₄ provides a sufficiently high density of trapping sites. This charge trapping stack consisting of SiO₂ (TO)-Si₃N₄ (CTL)-SiO₂ (BO) tri-layer is usually referred to as an ONO stack. The ONO suffers from the trade-off between programming speed and retention. On the one hand, to enhance program/erase (P/E) speed, a thinner TO is required. On the other hand, thicker TO ensures better retention. The implementation of high-k materials in CTF is expected to overcome some of the problems arising from the down-scaling of CTF and extend the applicability of this technology ^[15].

2. Tunneling and Blocking Oxides

Blocking and tunnelling oxides are also important parts of the charge trapping stack. As mentioned above, in the current CTFs, SiO₂ is used both as TO and BO. However, with the scaling of CTF cell dimensions, the thickness of TO and BO are also scaled-down, and the direct tunneling current through the thin tunnel SiO₂ layer deteriorates the retention characteristics. High-k dielectrics are also considered to replace SiO₂ as BO and TO. The use of material with a higher dielectric constant as a blocking layer ensures a lower electric field. Hence, carrier back-injection will be reduced. Substitution of tunnel SiO₂ by the high-k dielectric enables the use of physically thicker TO, which can improve retention performance. However, the TO should also be trap-free to avoid trap-assisted tunnelling of the stored charges through the TO. This requirement is not easy to satisfy as the high-k dielectrics are trap-rich materials. Among the high-k dielectrics, Al₂O₃ has the largest band gap (more than 8 eV). Hence, the band-offsets with the CTL and Si will be the largest, which ensures more efficient storage in the quantum well formed by the tri-layer (BO-CTL-TO). Al₂O₃ also has good chemical and thermal stability and it is CMOS compatible. Several studies have shown that Al₂O₃ as BO improves the memory window, retention parameters and P/E efficiency and mitigates the problem of erase saturation ^[16]^[17]^[18]. Recently, all- AlO_x CTF stack in which BO, TO and CTL are engineered using different gas ratios and pulse times of the ALD process to obtain AlO_x layers with different thicknesses and oxygen content has been demonstrated ^[19].

Two different CTLs were used in this case—nanolaminated stacks with 20 cy HfO₂ and 5 cy Al₂O₃ repeated five times (5×(20:5)) (Figure 3a) and doped samples with 4 cy HfO₂ and 1 cy Al₂O₃ repeated 25 times (25×(4:1)) (Figure 3b). Al₂O_3, as a tunnel and blocking oxide, enables the entire charge-trapping stack to be obtained in a single ALD deposition process, significantly simplifying the technology. The as-grown stacks with TO and BO, unlike stacks without TO and BO, demonstrate significant electron trapping. Hence, the memory window substantially increases (Figure 4a). It is seen that positive charge trapping depends on the tunnel oxide (and its thickness) and is weakly affected by the CTL.

Figure 3. Schematics of the memory capacitors with nanolaminated HfO₂/Al₂O₃ charge trapping stack (a) and Al–doped HfO₂ charge trapping stack (b) ^[20].

Figure 4. The flat band voltage shifts as a function of voltage pulse amplitude for different memory capacitor types: (a) before annealing; (b) after RTA in O₂. Red symbols correspond to +V_p and the blue symbols to −V_p ^[20].

On the contrary, the capture of electrons depends on the dielectric—it is stronger in the nanolaminated structures. It should be noticed that similarly to the as-deposited stacks without any TO and BO, the positive charge trapping increases progressively (almost linearly) with V_p, reaching very large values with no tendency for saturation. As discussed, such behaviour is explained by generating stress-induced positively charged defects. In structures with Al₂O₃ TO, regardless of the CTL, electron trapping is very weak, which makes them unsuitable as memory cells in CTF.

The impact of O₂ annealing (Figure 4b) is very similar to that observed for the structures without TO and BO—the trapping of electrons increases significantly, and the positive charge trapping decreases and exhibits a saturation. In other words, these results confirm that after RTA in O_2, the stacks are more resistant to high-electric-field degradation and no positive charge is generated. Consequently, the net positive charge trapping decreases, the net negative charge trapping increases and the two branches of the trapping characteristics become more symmetrical. It should also be noted that compared to as-deposited stacks, the electron and hole trappings start at lower V_p. Hence, the CTF can operate at lower voltages, which is one of the requirements the CTFs have to satisfy. The spatial density of trapped electrons, ρ_e, and holes, ρ_h, for various structures after RTA are calculated to be in the range ρ_h = (0.95–1.58) × 10¹⁹ cm⁻³ and ρ_e = (1.2–1.5) × 10¹⁹ cm⁻³ ^[20].

The retention characteristics of as-deposited stacks (Figure 5a) indicate that (i) the positive charge retention depends on the TO thickness and is independent of the dielectric stack; (ii) the discharge of positive charge follows a linear law which implies trap-to-band tunnelling mechanism; (iii) the discharge rate of positive charge is higher for stacks with thinner SiO₂, while for 3.5 nm SiO_2, the discharge rate is very low, i.e., 3.5 nm SiO₂ provides a good barrier to back-tunnelling of holes; (iv) the electron discharge follows different laws for the samples with 2.4 and 3.5 nm SiO₂. For thinner TO, retention characteristics are linear. Hence, the discharge is performed via trap-to-band tunnelling. For the thicker TO, the characteristics are well fitted by ln²(t), which implies electron detrapping via the Poole–Frenkel mechanism; (v) the electron discharge curves of the two types of CTL are parallel to each other at an equal thickness of TO. Hence, the electron traps in the two kinds of charge trapping layers have the same origin, but their density is higher in multilayered 5×(20:5) stacks.

Figure 5. Charge retention characteristics in capacitors with various HfO₂/Al₂O₃ stacks: (a) before and (b) after RTA in O₂; (c) 5×(20:5) stack without BO and TO after RTA. The red symbols correspond to a negative charge (respectively, positive values of V_fb) and the blue ones correspond to a positive charge (negative values of V_fb) ^[20].

Very significant changes in the discharge characteristics and their dependence on the parameters of the structure are provoked by O₂ annealing (Figure 5b). It should be mentioned that these changes are unexpected. Generally, the retention characteristics of stacks are deteriorated after annealing. In addition, the electron discharge rate is higher in structures with a thicker 3.5 nm SiO₂ than stacks with thinner 2.4 nm TO and slightly depends on the CTL. The discharge rate of holes is also higher after RTA and for thicker TO. Considering the obtained results ^[20] leads to the conclusion that the deteriorated characteristics are most likely due to a high-temperature-induced interaction between the HfO₂/Al₂O₃ charge trapping layer and the TO and the formation of defects due to this interaction. These defects, located at the CTL/TO interface and/or in the TO itself, cause a faster discharge of the charges stored in the CTL ^[21]. Defects generated by the annealing in the Al₂O₃ blocking oxide as a possible leakage path could not be rejected as well. As commented in ^[19], in Al₂O₃ deposited by ALD with H₂O as oxidant, different species such as Al-OH, Al-O-H, Al-Al could be formed, resulting in increased density of defects. The retention characteristics of the annealed 5×(20:5) stacks without any intentionally grown TO and BO (Figure 5c) support this conclusion—they are very similar to the retention in stacks with a thicker SiO₂ TO and BO before annealing. The endurance characteristics (Figure 6a) before annealing reveal instabilities, especially in electron trapping. Substantial degradation and progressive accumulation of positive charge have been observed for P/E cycles > 600. This supports the conclusion that the structures before RTA are vulnerable to high electric field stress degradation. After RTA in O_2, the structures demonstrate better endurance and can withstand more than 10⁴ P/E cycles without coming to breakdown (BD) (Figure 6b).

Figure 6. Endurance of BO/5×(20:5)/TO (3.5 nm SiO₂) capacitors before (a) and after O₂ annealing (b) measured under voltage pulses +/− 25 V. Red lines correspond to V_p = 25 V, blue ones to V_p= −25 V ^[20].

The obtained program and erase speeds are illustrated in Figure 7 for capacitors with 2.4 nm TO before and after oxygen annealing. The capacitors exhibit almost negligible electron trapping at pulses shorter than 10⁻⁴ s for the as-grown samples and 10⁻³ s for the annealed ones. In both cases, after the threshold pulse time, the electron accumulation in the CTL is rapid. The increase of pulse duration, t_p, within one decade results in the accumulation of more than 70% of the stored negative charge measured at t_p = 1 s. (The overall shape of the dependence ΔV_fb vs. t_p before and after annealing is the same—steep increase followed by a gradual increment with a tendency of saturation for t_p > 1 s). The detrapping of the captured electrons under negative V_p does not show abrupt change with the value of t_p. The more efficient electron release is observed at t_p above 10⁻⁵ s, and the full discharge state is reached at ~10⁻² s and 10⁻¹ s, for the as-grown and annealed stacks, respectively. The accumulation of positive charge in the CTL (“over-erasing”) requires pulse times about 100 times higher than the ones for the electron trapping under the same V_p magnitude. Hence, it can be concluded that the annealing increases the pulse duration (~10 times) needed to program the capacitor and return it to its initial state. This result agrees with the degradation of the retention characteristics after annealing and could be related to the defect generation in both the TO and BO layers. However, as demonstrated in ^[22], the inversion current of tunnel MOS capacitors on p-type substrates is dominated by the thermal generation rate of minority electrons via traps at the Si/SiO₂ interface and in the deep depletion region. Since the thermal generation at room temperature is slow, the measurements are conducted under illumination to neutralize this effect.

Figure 7. Dependence of the flat band voltage shifts for program and erase operations on the voltage pulse width, t_p for capacitors with BO and 2.4 nm TO, before and after annealing. The programming voltage is +25 V, and the erasing is −25 V.

It is helpful to compare the obtained results with the performance of conventional CT memory cells with the ONO stack. Ramkumar ^[15] reported very good endurance characteristics of poly-Si/oxide/nitride/oxide/Si (SONOS) cells with very small shifts of threshold voltage after 10⁶ P/E cycles. The retention in the erase state is also very good. However, in the program state at 85 °C, a significant loss of stored charge is observed (more than 50% at ten years). Similar stable retention performance in the erase state and faster detrapping rate in the program state demonstrate the stacks in Figure 5a. In Table 1, memory windows, program speeds and the time needed to reach the full window of ONO stacks reported in different works are given.

Table 1. Comparison of memory windows, program speeds and time to reach the full window of ONO stacks reported in different works.

Memory Window, V	Program Speed, s	Time to Full Window, s	Reference
5.5	10⁻⁵	10⁻¹	^[23]
2.5	3 × 10⁻⁵	10⁻¹	^[24]
5.5	10⁻⁵	10⁻¹	^[25]
8, on c-Si 10.7, on poly-Si	-	-	^[26]
6	10⁻⁵	10⁻¹	^[27]
4 cylindrical cell	10⁻⁷	10⁻³	^[28]^[29]

The memory windows of ONO structures are smaller than those of the HfO₂/Al₂O₃ stacks. The program speed of ONO stacks, however, is better—10⁻⁵ s. It should be mentioned that the excellent program speed of cylindrical cells with ONO stacks reported in ^[28]^[29] (Table 1) is due to hyperbolic dependence of the electric field along the radial coordinate, which enhances the field at the TO interface while decreasing it at BO interface. As mentioned, scaling rules and integration compatibility with CMOS process flow require the replacement of SONOS cells with MOHOS. Many works study charge trapping and storage in different MOHOS structures. Comparison of their properties could be considered only qualitatively because all performance characteristics depend very strongly on the materials used for the different layers in the charge trapping stack and the technology (including deposition technique, deposition parameters and annealing steps). For example, as shown by Agrawal et al. ^[19], even changing parameters of the deposition process (gas flow ratio and pulse deposition time of precursors) results in Al-oxide layers with substantially different properties in this way allowing the engineering of band-gap of the layer. What concerns ALD, the most widely used technology for high-quality quality, very thin high-k dielectric layers, the precursors used for the deposition process are also of utmost importance.

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Dencho Spassov

Albena Paskaleva

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1. Introduction

2. Tunneling and Blocking Oxides

References