Control systems engineering uses real-time models of power elements to perform verification. This allows for testing without risk of injuries or breaking down physical elements. This is called Hardware-in-the-Loop (HIL) testing.

A HIL model must be representative of the real item: it must deliver the same feedback in real-time and with high precision. This typically requires manually programming a Field Programmable Gate Array (FPGA) based system using a Hardware Description Language. But control engineers are more skilled in high-level approaches and prefer to use automated translation tools to generate the code. This requires less effort but in many cases generates less efficient models.

Researchers propose a design workflow that achieves manual-like performance using automatic translation. It adds three activities to the typical model generation flow:

• identification of similar operations
• forcing signal sign
• adjusting to multiplier input sizes

This can be applied both to models built from MATLAB code or from Simulink block designs.

Three different workflows are used to generate a HIL model of a buck converter. The sources of inefficiencies are located in the generated HDL code, which leads to the proposed workflow. This is then tested in a more complex model: a full-bridge converter with electrical losses using a Runge–Kutta method, with a pipelined operation.

The delivered code performs very close to a reference VHDL implementation. This is achieved both with MATLAB code and with Simulink block designs. This shows that control engineers can use the proposed workflow with no knowledge of VHDL to generate very efficient models, even for complex implementations.