1. Architecture

Block diagram of the i386 microarchitecture. https://handwiki.org/wiki/index.php?curid=1624970

The processor was a significant evolution in the x86 architecture, and extended a long line of processors that stretched back to the Intel 8008. The predecessor of the 80386 was the Intel 80286, a 16-bit processor with a segment-based memory management and protection system. The 80386 added a three-stage instruction pipeline, extended the architecture from 16-bits to 32-bits, and added an on-chip memory management unit. This paging translation unit made it much easier to implement operating systems that used virtual memory. It also offered support for register debugging.

The 80386 featured three operating modes: real mode, protected mode and virtual mode. The protected mode, which debuted in the 286, was extended to allow the 386 to address up to 4 GB of memory. The all new virtual 8086 mode (or VM86) made it possible to run one or more real mode programs in a protected environment, although some programs were not compatible.

The ability for a 386 to be set up to act like it had a flat memory model in protected mode despite the fact that it uses a segmented memory model in all modes was arguably the most important feature change for the x86 processor family until AMD released x86-64 in 2003.

Several new instructions have been added to 386: BSF, BSR, BT, BTS, BTR, BTC, CDQ, CWDE, LFS, LGS, LSS, MOVSX, MOVZX, SETcc, SHLD, SHRD.

Two new segment registers have been added (FS and GS) for general-purpose programs, single Machine Status Word of 286 grew into eight control registers CR0–CR7. Debug registers DR0–DR7 were added for hardware breakpoints. New forms of MOV instruction are used to access them.

Chief architect in the development of the 80386 was John H. Crawford.^[1] He was responsible for extending the 80286 architecture and instruction set to 32-bit, and then led the microprogram development for the 80386 chip.

The 80486 and P5 Pentium line of processors were descendants of the 80386 design.

1.1. Datatypes of 80386

The following data types are directly supported and thus implemented by one or more 80386 machine instructions; these data types are briefly described here.^[2]:

• Bit (boolean value), bit field (group of up to 32 bits) and bit string (up to 4 Gbit in length).
• 8-bit integer (byte), either signed (range −128..127) or unsigned (range 0..255).
• 16-bit integer, either signed (range −32,768..32,767) or unsigned (range 0..65,535).
• 32-bit integer, either signed (range −2³¹..2³¹−1) or unsigned (range 0..2³²−1).
• 64-bit integer, either signed (range −2⁶³..2⁶³−1) or unsigned (range 0..2⁶⁴−1).
• Offset, a 16- or 32-bit displacement referring to a memory location (using any addressing mode).
• Pointer, a 16-bit selector together with a 16- or 32-bit offset.
• Character (8-bit character code).
• String, a sequence of 8-, 16- or 32-bit words (up to 4 Gbit in length).^[3]
• BCD, decimal digits (0..9) represented by unpacked bytes.
• Packed BCD, two BCD digits in one byte (range 0..99).

2. Example Code

The following 80386 assembly source code is for a subroutine named _strtolower that copies a null-terminated ASCIIZ character string from one location to another, converting all alphabetic characters to lower case. The string is copied one byte (8-bit character) at a time.

 00000000 00000000 55 00000001 89 E5 00000003 8B 75 0C 00000006 8B 7D 08 00000009 8A 06 0000000B 46 0000000C 3C 41 0000000E 7C 06 00000010 3C 5A 00000012 7F 02 00000014 04 20 00000016 88 07 00000018 47 00000019 3C 00 0000001B 75 EC 0000001D 5D 0000001E C3 0000001F 

; _strtolower: ; Copy a null-terminated ASCII string, converting ; all alphabetic characters to lower case. ; ; Entry stack parameters ; [ESP+8] = src, Address of source string ; [ESP+4] = dst, Address of target string ; [ESP+0] = Return address ; _strtolower proc push ebp ;Set up the call frame mov ebp,esp mov esi,[ebp+12] ;Set ESI = src mov edi,[ebp+8] ;Set EDI = dst loop mov al,[esi] ;Load AL from [src] inc esi ;Increment src cmp al,'A' ;If AL < 'A', jl copy  ; Skip conversion cmp al,'Z' ;If AL > 'Z', jg copy  ; Skip conversion add al,'a'-'A' ;Convert AL to lowercase copy mov [edi],al ;Store AL to [dst] inc edi ;Increment dst cmp al,0 ;If AL <> 0, jne loop  ; Repeat the loop done pop ebp ;Restore the prev call frame ret ;Return to caller end proc

The example code uses the EBP (base pointer) register to establish a call frame, an area on the stack that contains all of the parameters and local variables for the execution of the subroutine. This kind of calling convention supports reentrant and recursive code and has been used by Algol-like languages since the late 1950s. A flat memory model is assumed, specifically, that the DS and ES segments address the same region of memory.

3. Chip Variants

3.1. 80386SX

A surface-mount version of Intel 80386SX processor in a Compaq Deskpro computer. It is non-upgradable unless hot air circuit board rework is performed. https://handwiki.org/wiki/index.php?curid=1463935

Die of Intel 80386SX. https://handwiki.org/wiki/index.php?curid=1446030

80386SL from 1990. https://handwiki.org/wiki/index.php?curid=1879165

In 1988, Intel introduced the 80386SX, most often referred to as the 386SX, a cut-down version of the 80386 with a 16-bit data bus mainly intended for lower-cost PCs aimed at the home, educational, and small-business markets, while the 386DX remained the high-end variant used in workstations, servers, and other demanding tasks. The CPU remained fully 32-bit internally, but the 16-bit bus was intended to simplify circuit-board layout and reduce total cost.^[4] The 16-bit bus simplified designs but hampered performance. Only 24 pins were connected to the address bus, therefore limiting addressing to 16 MB,^[5] but this was not a critical constraint at the time. Performance differences were due not only to differing data-bus widths, but also due to performance-enhancing cache memories often employed on boards using the original chip.

The original 80386 was subsequently renamed 80386DX to avoid confusion. However, Intel subsequently used the "DX" suffix to refer to the floating-point capability of the 80486DX. The 80387SX was an 80387 part that was compatible with the 386SX (i.e. with a 16-bit databus). The 386SX was packaged in a surface-mount QFP and sometimes offered in a socket to allow for an upgrade.

3.2. i386SL

The i386SL was introduced as a power-efficient version for laptop computers. The processor offered several power-management options (e.g. SMM), as well as different "sleep" modes to conserve battery power. It also contained support for an external cache of 16 to 64 kB. The extra functions and circuit implementation techniques caused this variant to have over 3 times as many transistors as the i386DX. The i386SL was first available at 20 MHz clock speed,^[6] with the 25 MHz model later added.^[7]

4. Business Importance

The first company to design and manufacture a PC based on the Intel 80386 was Compaq. By extending the 16/24-bit IBM PC/AT standard into a natively 32-bit computing environment, Compaq became the first third party to implement a major technical hardware advance on the PC platform. IBM was offered use of the 80386, but had manufacturing rights for the earlier 80286. IBM therefore chose to rely on that processor for a couple more years. The early success of the Compaq 386 PC played an important role in legitimizing the PC "clone" industry and in de-emphasizing IBM's role within it.

Prior to the 386, the difficulty of manufacturing microchips and the uncertainty of reliable supply made it desirable that any mass-market semiconductor be multi-sourced, that is, made by two or more manufacturers, the second and subsequent companies manufacturing under license from the originating company. The 386 was for a time (4.7 years) only available from Intel, since Andy Grove, Intel's CEO at the time, made the decision not to encourage other manufacturers to produce the processor as second sources. This decision was ultimately crucial to Intel's success in the market. The 386 was the first significant microprocessor to be single-sourced. Single-sourcing the 386 allowed Intel greater control over its development and substantially greater profits in later years.

AMD introduced its compatible Am386 processor in March 1991 after overcoming legal obstacles, thus ending Intel's 4.7-year monopoly on 386-compatible processors. From 1991 IBM also manufactured 386 chips under license for use only in IBM PCs and boards.

5. Compatibles

Intel i386 packaged by IBM. https://handwiki.org/wiki/index.php?curid=1715889

• The AMD Am386SX and Am386DX were almost exact clones of the 80386SX and 80386DX. Legal disputes caused production delays for several years, but AMD's 40 MHz part eventually became very popular with computer enthusiasts as a low-cost and low-power alternative to the 25 MHz 486SX. The power draw was further reduced in the "notebook models" (Am386 DXL/SXL/DXLV/SXLV), which could operate with 3.3 V and were implemented in fully static CMOS circuitry.
• Chips and Technologies Super386 38600SX and 38600DX were developed using reverse engineering. They sold poorly, due to some technical errors and incompatibilities, as well as their late appearance on the market. They were therefore short-lived products.
• Cyrix Cx486SLC/Cx486DLC could be (simplistically) described as a kind of 386/486 hybrid chip that included a small amount of on-chip cache. It was popular among computer enthusiasts but did poorly with OEMs. The Cyrix Cx486SLC and Cyrix Cx486DLC processors were pin-compatible with 80386SX and 80386DX respectively. These processors were also manufactured and sold by Texas Instruments.
• IBM 386SLC and 486SLC/DLC were variants of Intel's design which contained a large amount of on-chip cache (8 kB, and later 16 kB). The agreement with Intel limited their use to IBM's own line of computers and upgrade boards only, so they were not available on the open market.

6. Early Problems

Intel originally intended for the 80386 to debut at 16 MHz. However, due to poor yields, it was instead introduced at 12.5 MHz.

Early in production, Intel discovered a marginal circuit that could cause a system to return incorrect results from 32-bit multiply operations. Not all of the processors already manufactured were affected, so Intel tested its inventory. Processors that were found to be bug-free were marked with a double sigma (ΣΣ), and affected processors were marked "16 BIT S/W ONLY". These latter processors were sold as good parts, since at the time 32-bit capability was not relevant for most users. Such chips are now extremely rare and became collectible.

The i387 math coprocessor was not ready in time for the introduction of the 80386, and so many of the early 80386 motherboards instead provided a socket and hardware logic to make use of an 80287. In this configuration the FPU operated asynchronously to the CPU, usually with a clock rate of 10 MHz. The original Compaq Deskpro 386 is an example of such design. However, this was an annoyance to those who depended on floating-point performance, as the performance advantages of the 80387 over the 80287 were significant.

• 

  A very early 80386 at 12 MHz (A80386-12), before the 32-bit multiply bug was found. https://handwiki.org/wiki/index.php?curid=1399318

• 

  An A80386-16 marked "16 BIT S/W ONLY" with the multiply bug. https://handwiki.org/wiki/index.php?curid=1985713

• 

  A bug-free A80386-16 marked "ΣΣ". https://handwiki.org/wiki/index.php?curid=1539295

7. Pin-compatible Upgrades

Typical 386 upgrade CPUs from Cyrix and Texas Instruments. https://handwiki.org/wiki/index.php?curid=1154408

Intel later offered a modified version of its 80486DX in 80386 packaging, branded as the Intel RapidCAD. This provided an upgrade path for users with 80386-compatible hardware. The upgrade was a pair of chips that replaced both the 80386 and 80387. Since the 80486DX design contained an FPU, the chip that replaced the 80386 contained the floating-point functionality, and the chip that replaced the 80387 served very little purpose. However, the latter chip was necessary in order to provide the FERR signal to the mainboard and appear to function as a normal floating-point unit.

Third parties offered a wide range of upgrades, for both SX and DX systems. The most popular ones were based on the Cyrix 486DLC/SLC core, which typically offered a substantial speed improvement due to its more efficient instruction pipeline and internal L1 SRAM cache. The cache was usually 1 kB, or sometimes 8 kB in the TI variant. Some of these upgrade chips (such as the 486DRx2/SRx2) were marketed by Cyrix themselves, but they were more commonly found in kits offered by upgrade specialists such as Kingston, Evergreen and Improve-It Technologies. Some of the fastest CPU upgrade modules featured the IBM SLC/DLC family (notable for its 16 kB L1 cache), or even the Intel 486 itself. Many 386 upgrade kits were advertised as being simple drop-in replacements, but often required complicated software to control the cache or clock doubling. Part of the problem was that on most 386 motherboards, the A20 line was controlled entirely by the motherboard with the CPU being unaware, which caused problems on CPUs with internal caches.

Overall, it was very difficult to configure upgrades to produce the results advertised on the packaging, and upgrades were often not very stable or not fully compatible.

8. Models and Variants

8.1. Early 5 V Models

80386DX

Intel 80386DX, 25 MHz. https://handwiki.org/wiki/index.php?curid=1106518

Original version, released in October 1985.

• Capable of working with 16- or 32-bit external busses
• Cache: depends on mainboard
• Package: PGA-132 or PQFP-132
• Process: First types CHMOS III, 1.5 µm, later CHMOS IV, 1 µm
• Die size: 104 mm² (ca. 10 mm × 10 mm) in CHMOS III and 39 mm² (6 mm × 6.5 mm) in CHMOS IV.
• Transistor count: 275,000^[8]
• Specified max clock: 12 MHz (early models), later 16, 20, 25 and 33 MHz

80386SX 16 MHz. https://handwiki.org/wiki/index.php?curid=1817902

RapidCAD

A specially packaged Intel 486DX and a dummy floating point unit (FPU) designed as pin-compatible replacements for an Intel 80386 processor and 80387 FPU.

8.2. Versions for Embedded Systems

80376

This was an embedded version of the 80386SX which did not support real mode and paging in the MMU.

i386EX, i386EXTB and i386EXTC

Intel i386EXTC, 25 MHz. https://handwiki.org/wiki/index.php?curid=1585907

System and power management and built in peripheral and support functions: Two 82C59A interrupt controllers; Timer, Counter (3 channels); Asynchronous SIO (2 channels); Synchronous SIO (1 channel); Watchdog timer (Hardware/Software); PIO. Usable with 80387SX or i387SL FPUs.

• Data/address bus: 16 / 26 bits
• Package: PQFP-132, SQFP-144 and PGA-168
• Process: CHMOS V, 0.8 µm
• Specified max clock:
  • i386EX: 16 MHz @2.7~3.3 volt or 20 MHz @3.0~3.6 volt or 25 MHz @4.5~5.5 volt
  • i386EXTB: 20 MHz @2.7~3.6 volt or 25 MHz @3.0~3.6 volt
  • i386EXTC: 25 MHz @4.5~5.5 volt or 33 MHz @4.5~5.5 volt

i386CXSA and i386SXSA (or i386SXTA)

Intel i386CXSA, 25 MHz. https://handwiki.org/wiki/index.php?curid=1108706

Transparent power management mode, integrated MMU and TTL compatible inputs (only 386SXSA). Usable with i387SX or i387SL FPUs.

• Data/address bus: 16 / 26 bits (24 bits for i386SXSA)
• Package: BQFP-100
• Voltage: 4.5~5.5 volt (25 and 33 MHz); 4.75~5.25 volt (40 MHz)
• Process: CHMOS V, 0.8 µm
• Specified max clock: 25, 33, 40 MHz

i386CXSB

Transparent power management mode and integrated MMU. Usable with i387SX or i387SL FPUs.

• Data/address bus: 16 / 26 bits
• Package: BQFP-100
• Voltage: 3.0 volt (16 MHz) or 3.3 volt (25 MHz)
• Process: CHMOS V, 0.8 µm
• Specified max clock: 16, 25 MHz

The content is sourced from: https://handwiki.org/wiki/Engineering:Intel_80386