SiC Trench MOSFETs’ Reliability under Short-Circuit Conditions

SiC Trench MOSFETs’ Reliability under Short-Circuit Conditions: History

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MOSFET 在不同的直流总线电压下表现出不同的故障模式。对于双沟槽 SiC MOSFET，故障模式是较低直流总线电压下的栅极故障和较高直流总线电压下的热失控，而非对称沟槽 SiC MOSFET 的故障模式分别是软故障和热失控。非对称沟槽 MOSFET 的短路耐受时间 (SCWT) 高于双沟槽 MOSFET。对短路测试期间器件内部的热应力和机械应力进行了模拟，以探究故障机制并揭示器件结构对器件可靠性的影响。最后，进行了故障后分析，验证了设备故障的根本原因。

SiC trench MOSFET
short-circuit failure mechanism
failure analysis

一、简介

在过去的几十年里，与传统的硅器件相比，像 SiC 这样的宽带隙半导体由于其高击穿场、高热导率和宽带隙 [ 1 , 2 ] 而变得更具吸引力。目前，肖特基二极管等iC器件得到了快速发展，并在商业上得到广泛应用[ 3 , 4 ]。然而，与 Si-IGBT 相比，SiC MOSFET 的短路性能仍然较差。由于其更小的面积和更高的功率密度，SiC MOSFET 具有比 Si-IGBT 更高的结温，并且容易遭受热失控 [ 5 , 6 , 7 , 8]。此外，SiC MOSFET 的界面态较差问题也会导致栅极可靠性问题，从而导致器件栅极失效 [ 9 , 10 ]。

随着 SiC 材料生长和器件制造技术的发展，SiC MOSFET 的结构变得越来越复杂。今天，可以使用来自不同制造商的各种具有平面和沟槽栅极结构的商用 SiC MOSFET [ 11、12 ]。与 SiC 平面栅极 MOSFET 相比，沟槽栅极 MOSFET 具有更高的功率密度和更低的导通电阻 [ 13 ]。尽管 SiC 沟槽 MOSFET 具有许多优点，但由于制造过程中引入的缺陷，其可靠性需要进一步研究 [ 14 ]。首先，栅极形成过程中氧化的不均匀性使得侧壁和沟槽底部的氧化层厚度不一致。氧化不一致性增加了SiO

_{2}

/SiC 表面粗糙度，并导致粗糙点处局部电场集中。因此，更多的电荷注入到栅氧化层，增加了通过栅氧化层的电荷，缩短了介质击穿的时间[ 15 , 16 ]。否则，螺纹位错（螺纹位错 (TSDs) 和螺纹刃位错 (TEDs)）会导致器件中出现明显的泄漏点，从而严重降低 SiC 器件的性能 [ 17 , 18]。第二个问题是臭名昭著的接口状态问题。此外，SiC器件往往工作在高电压条件下，这使得栅氧化层承受高电场。作为回应，已经提出了不同的屏蔽方法，例如双沟槽 MOSFET (DT-MOSFET) 和非对称沟槽 MOSFET (AT-MOSFET) [ 19 , 20 ]。DT-MOSFET 的短路故障模式已被详细报道 [ 21 , 22 ]，而 AT-MOSFET 的短路可靠性研究较少。已经报道了两种器件的短路可靠性比较[ 23]，但更侧重于设备故障模式的安全工作区域和故障预测。与器件结构差异相关的短路过程中内部热应力和机械应力的差异尚未得到解决。

2. 设备结构和实验设置

2.1。设备结构

The short-circuit reliability of two 1200 V SiC commercial power trench MOSFETs manufactured by Rohm and Infineon, respectively, have been chosen as the devices under test (DUTs) [24,25]. The main electrical parameters of the devices have been listed in Table 1. Figure 1 shows the cell structure of two devices. The structure parameters of the devices have been obtained by SEM and FIB, as shown in Figure 2. The doping concentrations of the device have been obtained by fitting the device characteristics (transfer curve, output curve, breakdown voltage, etc.) by the numerical simulation.

Figure 1. Cross-section images of the two trench MOSFETs. (a) DT-MOSFET. (b) AT-MOSFET.

Figure 2. Cross-section images of the two trench MOSFETs by FIB and SEM. (a) DT-MOSFET. (b) AT-MOSFET.

Table 1. Device rated parameters.

2.2. Experiment Setup

Figure 3 shows the short-circuit test circuit schematic diagram and the photograph of the test platform. To provide sufficient energy during the short-circuit, C1 consisted of six 50

μ

F/1200 V capacitors [26]. In order to avoid device catastrophic failure, an IGBT [27] was employed as the solid-state circuit breaker. Initially, both the IGBT and the DUT were kept off. At first, S1 was turned on and the capacitor C1 was charged to a high voltage via a DC power supply. Afterwards, S1 was turned off and the short-circuit stress was applied to the DUT. The short-circuit pulse width was varied by controlling the gate signals of the IGBT and the DUT. The short-circuit capability of the device can be quantified by the short-circuit withstand time (SCWT), reflecting the maximum short-circuit time that the device can tolerate. After every single test, the device was cooled down to room temperature before the next test started to prevent the heat accumulation inside the devices.

Figure 3. Circuit schematic diagram: (a) Simplified schematic of the short-circuit test. (b) Photograph of the test platform.

3. Experiment Results

3.1. DT-MOSFET

Figure 4 shows typical experimental short-circuit waveforms of SiC DT-MOSFETs with VDC = 300 V and VGS = 18 V/−3 V. When the device is turned on, internal parasitic parameters of the device and the test board cause a brief overshoot on V $_{G S}$ and V $_{D S}$ . However, this overshoot does not affect the following short-circuit process [28]. The short circuit pulse width $t_{s c}$ sc was gradually increased to 28 $μ$ s until the device reached the failure point, accompanied by a peak current value of 125 A and a V $_{G S}$ drop of 2.5 V. The anomaly only showed on the gate voltage waveform, manifested as a sudden increase of V $_{G S}$ (from −3 V to 0 V) after the device has been turned off for 7 $μ$ s, whereby the drain-source voltage still maintained to DC bus voltage. This means that the gate and source terminals are shorted, while the drain-source body diode still has blocking capability. The measured waveforms indicate the gate failure mode[10,29,30]. The same result was demonstrated in the subsequent electrical inspection of the three terminals, as shown in Table 2.

Figure 4. Short-circuit failure waveforms for the SiC DT-MOSFETs at 300 V DC bus voltage.

Table 2. DT-MOSFET: Measured resistances between electrodes before and after tests.

Figure 5 shows the short-circuit waveforms of SiC DT-MOSFETs measured before the failure (a) and at the failure (b), when increasing the bus voltage to 600 V. Higher DC bus voltage leads to higher power dissipation, causing the SCWT to decrease to 7

μ

s. When the device fails, the peak current value is about 135 A, accompanied by the V $_{G S}$ drop of about 1 V. It can be seen from Figure 5b that a significant trail current appears after the device is turned off, climbing up to 39 A. High junction temperature caused by high power consumption can significantly increase the carrier density. Therefore, the device cannot be completely shut down at the end of short-circuit operation [31]. The hole current is the main cause of tail currents. Due to the existence of the tail current, more heat is generated, forming a positive feedback. If the tail current exceeds the threshold current to trigger the parasitic BJT, the hole density and the junction temperature will increase further and finally lead to thermal runaway [32]. As listed in Table 2, the resistance between the three terminals (R $_{G S}$ , R $_{G D}$ , and R $_{D S}$ ) after the short-circuit test became quite low, revealing that all electrodes were shorted.

Figure 5. Short-circuit waveforms for the SiC DT-MOSFETs at 600 V DC bus voltage. (a) Last waveforms before failure and (b) failure.

3.2. AT-MOSFET

Figure 6 shows typical experimental short-circuit waveforms of SiC AT-MOSFETs at 300 V DC bus voltages, and gate bias was set as VGS = 18 V/−3 V. Under the same conditions, the SiC AT-MOSFET shows better short-circuit performance than the DT-MOSFET (35 μs for AT-MOSFET, 28 μs for DT-MOSFET). Under the same conditions, the SiC AT-MOSFET shows better short-circuit performance than the DT-MOSFET (35 $μ$ s for AT-MOSFET, 28 $μ$ s for DT-MOSFET). However, the longer short-circuit time leads to more serious device damage. After withstanding a 35 $μ$ s short-circuit pulse, the device is no longer able to operate normally. First, the short-circuit current drops to a dozen amps and shows an abnormal upward trend. In addition, the gate voltage is 9 V/−2 V even external 18 V/−3 V is applied. This indicates that a leakage path is formed between the gate and source, but they are not completely shorted, which is referred to as the soft failure. Devices have been previously reported to fail at low bus voltages due to gate-source SiO $_{2}$

rupture [33]. Therefore, it can be inferred that the gradual accumulation of dielectric layer damage in AT-MOSFETs under prolonged short-circuit stress may be the root cause of soft failure. The device body diode is still able to carry 300 V. The results of the subsequent electrical inspection of the three terminals are shown in Table 3.

Figure 6. Short-circuit failure waveforms for the SiC AT-MOSFETs at 300 V DC bus voltage.

Table 3. AT-MOSFET: Measured resistances between electrodes before and after tests.

Figure 7 shows short-circuit waveforms of SiC AT-MOSFETs at 600 V DC bus voltages, and gate bias was set as VGS = 18 V/−3 V. At higher bus voltage, the device is subjected to higher power dissipation and the AT-MOSFET exhibits a thermal runaway mode after a 8.5 μs SC pulse. At higher bus voltage, the device is subjected to higher power dissipation and the AT-MOSFET exhibits a thermal runaway mode after a 8.5 $μ$ s SC pulse. The performance is slightly better than that of DT-MOSFETs, but it is somewhat different from the thermal runaway mode of DT-MOSFETs. First, the thermal runaway of the AT-MOSFETs does not occur after the device is turned off, but during the period when the short-circuit stress is applied. A comparison with the last waveforms measured before failure shows that the current increases during the short-circuit pulse. For example, the drain current increased from 66 A to 78 A at 7 $μ$ s. This indicates that a trailing current has occurred during the short-circuit pulse. As the junction temperature increases further, the current value is sufficient to trigger the parasitic BJT before the device shuts down. Compared to the DT-MOSFETs, the higher power level of the AT-MOSFET results in a higher peak current than the DT-MOSFETs, making the junction temperature rise faster, thus causing the thermal runaway mode to be triggered before the device is turned off. The second point is that the gate-source voltage of the AT-MOSFETs exhibites anomalies during the short-circuit pulse. There is a gate voltage drop of about 4 V near the point of failure, indicating that a high leakage current is flowing across the gate resistance. This indicates that the gate degradation occurs also. However, the junction temperature rises rapidly due to the higher bus voltage, so that there is not enough time for the gate to be damaged seriously before the thermal runaway occurs. The electrical characteristics in 表 3还显示器件的所有三个端子都短接在一起。

图 7. 600 V DC 总线电压下 SiC AT-MOSFET 的短路波形。( a ) 故障前测量的最后波形和 ( b ) 故障时测量的波形。

SCWT 的结果和 DUT 之间的提取 Pmax 比较如图 8所示。短路测试中消耗的最大功率更高，因为 AT-MOSFET 的额定电流高于 DT-MOSFET。但DT-MOSFET在不同母线电压下的存活时间比AT-MOSFET短，有待进一步研究。

图 8.不同 DUT 在不同条件下的SCWT 和提取的 $P_{\max}$ 比较。

This entry is adapted from the peer-reviewed paper 10.3390/ma15020598

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