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Memristor-Based Logic Circuits: Concept and Prospect: History
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Contributor:
Zhipeng Liao
, Abusaleh Jabir ,
Guangyu Xue
, Zohreh Hajiabadi ,
Vihirthan Ravitharan
, Sridhar Chandrasekaran , Firman M. Simanjuntak

As computational demands from artificial intelligence increase, traditional von Neumann architectures face memory wall bottlenecks while CMOS technology approaches physical limitations defined by Moore’s law and Dennard scaling. This entry examines memristor-based logic circuits as potential solutions to overcome these computing constraints. We systematically analyse various memristor-based logic implementation approaches by reviewing and comparing stateful methods, including Material Implication (IMPLY) and Memristor-Aided Logic (MAGIC), as well as non-stateful techniques such as Memristor-Ratioed Logic (MRL) and Scouting Logic (SL). Each approach demonstrates unique capabilities for implementing fundamental logic operations, with progressive improvements in efficiency documented across multiple research studies. We discuss that while memristor-based logic shows promise, significant limitations exist: crossbar arrays can only integrate specific gates (NOT, NOR), MAGIC architecture struggles with multilevel cascade and large fan-out circuits, IMPLY requires numerous operational steps, and MRL faces challenges integrating CMOS-based inverters into crossbars.

  • memristor
  • logic gates
  • IMPLY
  • MAGIC
  • MRL
  • SL
With the intelligent revolution sweeping the world, we have entered the era of artificial intelligence in the 21st century. AI machines that use fully neural network models may require high computational complexity and computational power [1]. The improvement of hardware computing power relies on its logic gates, where its innovation is strongly dependent on CMOS architecture and fabrication; however, classical logic gate designs cannot keep up with Moore’s law [2] and Dennard scaling [3]. Moreover, today’s von Neumann computer architecture suffers from a data transmission bottleneck, where the computing speed is further limited by how fast the data can flow back and forth between the storage unit and the computing unit [4]. Such frequent data movement is accompanied by considerable energy consumption and is therefore inefficient [5]. The emergence of non-von Neumann architectures, such as quantum and neuromorphic computing, offers a promising solution to overcome the limitations of today’s computing speed and power efficiency [4][6].
Nevertheless, these emerging computer architectures still require logic gates to run the peripheral circuitry, for which today’s classical logic gate designs are often not suitable to support low-power computing hardware, especially when they need to be operated in extreme environments, e.g., cryogenic and high-energy radiation ambient; this is due to transistors not performing well in these environments [7][8]. These considerations have stimulated interest in emerging switching devices, especially memristors, for constructing compact and low-power logic circuits with reduced transistor overhead [6]. The memristor was originally postulated by Chua as the fourth fundamental passive circuit element relating charge and flux [9], and was later physically realised in nanoscale resistive-switching devices [10], which triggered extensive research into memristor-based memory, neuromorphic hardware, and logic architectures [6][11].
Among all arithmetic logic operations, addition serves as the foundation for all computational operations. Both subtraction and multiplication can be achieved through the concatenation of adders or by taking the two’s complement, while division can be constructed using the intersections of subtracters and adders. Further, in the binary domain, addition can be broken down into multiple logical operations, allowing the use of logic gates to build an adder. Modern digital systems commonly use two well-defined states in CMOS circuits to represent logic 1 and logic 0, and then construct arithmetic modules based on Boolean operations. In memristor devices, logic states can similarly be encoded by the high-resistance state (HRS) and low-resistance state (LRS), creating the possibility of implementing logic using resistance switching rather than only transistor-based voltage switching [12][13].
In 2012, S. Kvatinsky et al. [12], proposed the construction of OR and AND gates using two different states of high and low resistance of a memristor to represent logic 1 and logic 0. Since then, several major families of memristor-based logic have been developed. From a circuit perspective, these schemes can be broadly divided into stateful logic, where logical operands and results are stored as resistance states in the devices, and non-stateful logic, where the output is represented by voltage or current and interpreted by peripheral circuitry or sensing structures. Representative stateful families include IMPLY logic and MAGIC, whereas representative non-stateful or read-based families include MRL and Scouting Logic. More recent studies have further extended the field from primitive gate demonstrations to experimentally validated and reconfigurable logic-in-memory and arithmetic implementations [14][15][16][17][18]. Therefore, this entry discusses the conceptual development of memristor-based logic circuits, compares their representative operating styles, and summarises their limitations and future prospects.

This entry is adapted from the peer-reviewed paper https://doi.org/10.3390/encyclopedia6090190

References

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  2. Moore, G.E. Cramming more components onto integrated circuits. Proc. IEEE 1998, 86, 82–85.
  3. Dennard, R.H.; Gaensslen, F.H.; Hwa-Nien, Y.U.; Leo Rideout, V.; Bassous, E.; Leblanc, A.R. Design of Ion-Implanted MOSFETs with Very Small Physical Dimensions. Proc. IEEE 1999, 87, 668–678.
  4. Di Ventra, M.; Pershin, Y.V. The parallel approach. Nat. Phys. 2013, 9, 200–202.
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  6. Xiao, Y.; Jiang, B.; Zhang, Z.; Ke, S.; Jin, Y.; Wen, X.; Ye, C. A review of memristor: Material and structure design, device performance, applications and prospects. Sci. Technol. Adv. Mater. 2023, 24, 2162323.
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  8. Prinzie, J.; Simanjuntak, F.M.; Leroux, P.; Prodromakis, T. Low-power electronic technologies for harsh radiation environments. Nat. Electron. 2021, 4, 243–253.
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  10. Strukov, D.B.; Snider, G.S.; Stewart, D.R.; Williams, R.S. The missing memristor found. Nature 2008, 453, 80–83.
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  12. Kvatinsky, S.; Wald, N.; Satat, G.; Kolodny, A.; Weiser, U.C.; Friedman, E.G. MRL-Memristor Ratioed Logic. In Proceedings of the 2012 13th International Workshop on Cellular Nanoscale Networks and Their Applications, Turin, Italy, 29–31 August 2012; pp. 1–6.
  13. Borghetti, J.; Snider, G.S.; Kuekes, P.J.; Yang, J.J.; Stewart, D.R.; Williams, R.S. Memristive switches enable stateful logic operations via material implication. Nature 2010, 464, 873–876.
  14. Wang, Z.; Li, Y.; Su, Y.; Zhou, Y.; Cheng, L.; Chang, T.-C.; Xue, K.-H.; Sze, S.M.; Miao, X. Efficient Implementation of Boolean and Full-Adder Functions with 1T1R RRAMs for Beyond Von Neumann In-Memory Computing. IEEE Trans. Electron Devices 2018, 65, 4659–4666.
  15. Cheng, L.; Li, Y.; Yin, K.; Hu, S.; Su, Y.; Jin, M.; Wang, Z.; Chang, T.; Miao, X. Functional Demonstration of a Memristive Arithmetic Logic Unit (MemALU) for In-Memory Computing. Adv. Funct. Mater. 2019, 29, 1905660.
  16. Hoffer, B.; Rana, V.; Menzel, S.; Waser, R. Experimental Demonstration of Memristor-Aided Logic (MAGIC) Using Valence Change Memory (VCM). IEEE Trans. Electron Devices 2020, 67, 3115–3122.
  17. Song, Y.; Wang, X.; Wu, Q.; Yang, F.; Wang, C.; Wang, M. Reconfigurable and Efficient Implementation of 16 Boolean Logics and Full-Adder Functions with Memristor Crossbar for Beyond von Neumann In-Memory Computing. Adv. Sci. 2022, 9, 2200036.
  18. Youn, S.; Lee, J.; Kim, S.; Park, J.; Kim, K.; Kim, H. Programmable Threshold Logic Implementations in a Memristor Crossbar Array. Nano Lett. 2024, 24, 3581–3589.
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