CeO2 is considered the most promising candidate because of its multiple oxidation states (Ce3+ and Ce4+), remarkable resistive-switching (RS) uniformity in DC mode, gradual resistance transition, cycling endurance, long data-retention period, and utilization of the RS mechanism as a dielectric layer, thereby exhibiting potential for neuromorphic computing.
1. Introduction
To date, cerium oxide (CeO2) has been suggested as a promising candidate showing analog-switching behavior of memristors. Furthermore, several researchers have reported significant digital-type resistance variation for RRAM implementation using a ceria switching layer [14,15,16,17]. Ismail et al. [16] demonstrated the bipolar switching mechanism in Al/CeO2/Au and Zr/CeOx/Pt architectures. Lin et al. also presented the nonpolar switching behavior due to the polycrystalline CeO2 layer of a Pt/CeO2/Pt structure [17]. Remarkably, CeO2-based analog switching is still being researched. In this respect, the demonstration of analog-based switching of a Pt/CeO2/Pt memristor has been displayed in memristive technology. Moreover, Pt/CeO2/Pt analog synaptic devices also possess a symmetric electrode structure, thereby prominently exhibiting emulated synaptic trends in the form of potentiation and depression behaviors in computation. Therefore, its comprehensive switching peculiarities for artificial synapses have been extensively studied [18].
In addition, a Pt/ITO/CeO2/Pt memristive device and ITO behaving as a capping layer often play a vital role toward synaptic trends. The stability of analog resistance variation to emulate the potentiation and depression functions in an ITO free-layered Pt/CeO2/Pt memristor has been elaborately reported [18,20]. Further, the exhibited potentiation and depression dynamics of the Pt/CeO2/Pt memristor have shown nonlinearity and asymmetry instead of a symmetric architecture. Because it has a nonfilamentary route such as that of other memristors, this device also has the disadvantage of memory loss, which limits its stability in analog/multilevel synaptic weight modulation. However, a CeO2-based memristor having oxygen reactivity in an ITO electrode form exhibits enhanced conductivity caused by increased density of oxygen vacancies (OVs) [21].
Further, memristors are suggested as candidates for artificial synapses owing to comparable structures with presynaptic-neuron/synapse/postsynaptic-neuron architectures with higher density of neuromorphic synaptic systems. Furthermore, their resistance states always mimic analog synaptic weight functioning with a wide variety of synaptic dynamics, such as postsynaptic current, paired-pulse facilitation (PPF), short-term plasticity (STP), long-term plasticity (LTP), and spike-time-dependent plasticity (STDP) [22,23,24]. Herein, a promising analog synapse formation in the Pt/CeO2/Pt memristor under annealing of ceria layer has also been investigated to explore optimal effect of Pt/CeO2 interfacial states.
For the advancement in analog resistance variation in Pt/CeO2/Pt memristors, an approach involving altering the post-deposition annealing environment for changing the switching parameters of the CeO2 synapse-based layer has been widely studied. However, from the conduction mode investigation data and spectroscopic study of chemical-bonding states, the reference device was found to be capable of voltage-controlled operation due to Pt/CeO2 interfacial contacts [26].
Memristors have been extensively discussed as capable artificial synaptic devices owing to inheriting synaptic weight change into neural networks [13,18]. Moreover, synaptic plasticity can also be modulated by various input signals as synaptic functions. In this regard, various oxide-based nanomaterials, such as ZnO [30], Y2O3 [31], CeO2 [32,33,34], HfOx [35], and ZrO2 [36], have been proposed for memristive memories as well as synaptic type devices. Among them, CeO2 has been suggested as the most promising material for renewable nonvolatile memories, as it exhibits a high dielectric constant of ~26 and a high bandgap of 6 eV, which covers the maximum residual bandgap in other oxide materials [37]. The flexible valence states of Ce3+ and Ce4+ in ceria can create conducting filaments (CFs) containing OVs or may disrupt them upon application of a biasing voltage signal. Meanwhile, the versatile asymmetric electrode memristor Ag/CeO2/Pt has been widely examined. The resistance state-functioning of an active metal/oxide/inert metal structure was initially tuned by rupturing of the silver CF; moreover, the CF containing defective OVs was also comparatively studied [38]. The Ag/CeO2/Pt memristor has been demonstrated to be an inherent bipolar resistance switching device with the realization of slow variation in resistance states with low operating voltage, which has enabled artificial synapse simulation [39].
2. Filamentary Mechanisms in CeO2-Based Memristors
The RS mechanisms of various materials have been widely analyzed for elucidating the resistance variation process; however, the resistance switching mechanism in RRAMs is still contentious. Several literature reviews have been presented to understand switching kinetics in different switching materials. Interestingly, no specific switching mechanism assures 100% RS behavior [
1,
40]. However, the conductive filamentary mechanisms are broadly predictable, whereas major disagreements still prevail concerning microstates, configuration, and shape of the creation and annihilation of the CFs. Initially, one or multiple filaments, i.e., local conducting channels are formed or ruptured when an external stimulus is applied. Some materials may require a forming state with the application of external voltages. In this way, CFs may be created by the occurrence of soft break-up in the insulating layer [
41]. Therein, change from a high-resistance state (HRS) to a low-resistance state (LRS) corresponds to the SET process, whereas the converse variation represents the RESET process. Further, under application of a positive voltage at the top electrode (TE), charge carriers trapped by vacancies form a filamentary path, and the device goes into LRS. Conversely, during the reverse mechanism the device will occupy HRS. Akinaga H. stated that the thermally assisted redox reaction with anodization at the metal electrode and oxide-layer interface is responsible for the possible mechanisms [
42]. Usually, Joule heating is considered the leading cause of rupturing of conducting paths [
43]. However, the typical filamentary mechanism is generally not dependent upon the contact area associated with device electrodes [
44,
45].
2.1. Electrochemical Metallization Filamentary Mechanism
The basic working principle of RRAM cells is the basis for filamentary classification. The filamentary mechanism can be classified as electrochemical metallization mechanism (ECM), valence change mechanism (VCM) [
46], and thermochemical mechanism (TCM) [
47,
48].
2.1.1. Electrochemical Metallization Mechanism
ECM is often considered to elaborate the working principle of RRAM devices by using metals having high mobility for dynamic electrodes, such as silver (Ag), copper (Cu), and nickel (Ni) [3]. Yang et al. reported the conductive filament mechanism for the Pt/SiO2/Ag structure using transmission electron microscopy (TEM) [49]. For new planar architecture formation, conductive channels are not formed within the SiO2 layer lying between Ag and Pt electrodes. After application of a positive potential to the Ag electrode, an oxidation reaction occurs (Ag - e → Ag+). During the movement of Ag+ toward the Pt electrode surface, Ag+ loses electrons to undergo reduction and becomes Ag. The Ag provides evidence of Ag conductive filament formation in an RRAM switching layer, thereby exhibiting LRS. By contrast, upon application of a positive voltage at the Pt electrode, the HRS state of the device is observed, supporting the breakdown of the conducting path.
2.1.2. Valence Change Mechanism
VCM and ECM exhibit the same trends with respect to electrochemical reaction and ion mobility mechanisms. ECM is often considered as an electrochemical reaction involving active metals, whereas VCM is also electrochemical reaction, though it is based on O
Vs in oxide materials. Generally, the device resistance change is significantly affected by oxygen-related defects in electrochemical reactions. The extensive literature has reported that the transition between HRS and LRS corresponding to the desired memory device (such as RRAM) is caused by the damage or formation of O
V filaments [
3,
54,
55,
56,
57]. When positive biasing is applied at an inert TE, the oxide insulating layer becomes active in LRS; O
2− changes their original position, and the O
Vs alternatively produce a conductive path along with drifting toward the anode/oxide-layer interface. In this way, a conductive path containing O
Vs is eventually created, increasing the conductivity owing to the functional layer film.
2.1.3. Thermochemical Mechanism
RRAM cells commonly show resistance variation with the application of an electric field and Joule heating-based O
2− reactions associated with drifting that dominate the operation mechanism [
61]. In these RRAM cells, the forming process is attributable to thermal rupturing within the device medium and the subsequent formation of CFs. By contrast, the reset process corresponds to thermal melting of the dominant CFs [
62,
63]. Moreover, unipolar/bipolar modes are considered more effective in RRAM cells owing to the free Joule heating development without a polarity effect. The nonpolar switching in resistance change has exhibited a particular trend in some previous studies. Jung et al. demonstrated a Pt/NiO/Pt memory structure and discussed temperature-dependent resistance change in switching dynamics in NiO films, revealing the corresponding OFF-state current evaluated with respect to temperature and defect patterns.
3. Unipolar and Bipolar CeO2-Based Memristors
RRAM is a nonvolatile memory, showing two logical resistance states of the switching channel. It characteristically involves an insulating or semiconducting layer, mainly composed of high-k oxide nanomaterials sandwiched between two electrodes. These memory devices commonly exhibit hysteresis performance with current and voltage characteristics (i.e., negative differential resistance at a specific applied potential). In the SET state, when the applied voltage and current approach a threshold level, RRAM cells switch from the HRS (OFF-state) to the LRS (ON-state). Similarly, upon application of a specific voltage, the RRAM cells return to their OFF-state when the prevailing tendency is removed. In nonpolar RRAM, the SET and RESET modes work with unidirectional applied voltage. By contrast, in bipolar RRAM, the resistance may vary step-wise, showing two distinct values; however, some devices exhibit gradual resistance variation depending upon the previous path of charges [
68].
Sun et al. reported the bipolar switching mechanism in the Al/CeO
x/Pt cell associated with multilevel resistance variation through the creation and rupturing of CFs containing O
Vs by valence change from Ce
3+ to Ce
4+ cations [
14,
18]. Many researchers have demonstrated a digital-type resistance variation for RRAM applications by utilizing the CeO
2 switching layer [
14,
15,
16,
70] through typical I–V curves for the RS trend involving the TE area (0.25 mm
2), employing a sweeping voltage at 300 K.
Bipolar resistive switching (BRS) and unipolar resistive switching (URS) have been achieved in a double-layer Ag/Ti/CeO
2/Pt structure under different sweep rates along with CC. In BRS, the RS trend depends upon ECM, whereas TCM is dominated by URS functioning. No forming process and small RS voltage make the device more attractive [
39]. Here, a sweeping voltage mode associated with a sweeping potential (0.005 V) at a rate of 0.09 V/s is followed. Further, sweeping voltage operation in the order of 0 V → 1 V → −1 V → 0 V favors bipolar behavior of the device. The device shows the HRS of 2800 Ω with a sweeping potential of 0–1 V. Then, the resistance state changes to LRS, exhibiting 270 Ω at 0.3 V. In this case, the CC (1 mA) is observed. Negative biasing is dominated by CF [
72]. In addition, I–V curves exploring the space-charge-limited current (SCLC) obey Ohm’s law (I ∝ V) and Child’s law (I ∝ V
3/2).
By contrast, a current of 2 mA was set during SET state, whereby URS behavior was observed. Further, the current increased to 1.4 V and the resistance states changed to SET. Afterward, at a positive voltage (without limiting current), the device changed from LRS to HRS operating at a potential of 0.7 V (but without the forming step). TCM [73,74] was followed to explain the URS trend associated with the CFs during the LRS state. The local current density in the conductive channel becomes very large, resulting in Joule heating, which sharply raises the temperature of the conductive filament. Then, the conducting channel breaks while returning the device to a high resistance. Further, bipolar RS characteristics were explored in a bilayer TaN/CeO2/TiO2/Pt structure. The set voltage was found to be dominated by CeOx layer thickness, indicating the switching process to be an electric field-induced mechanism.
4. Threshold CeO2-Based Memristors
Threshold-switching-type memristors have become attractive for selectors of crossbar memory structures. The threshold switching memristor involving a single layer of CeO
2 transforms into a new memory over repeated cycles caused by an overgrowth of Ag filament, thereby changing the device to LRS. Hence, optimal threshold switching was suggested in the aforementioned diffusive memristors by taking CeO
2 as a switching layer composed of Ag filaments (with low voltage) combined with a SiO
2 diffusion barrier layer in controlling the filament formation to achieve an advanced memory device. In this respect, an amorphous-type SiO
2 layer was placed underneath the CeO
2 layer, behaving as an obstacle for the overgrowth of silver metal filaments and thereby enhancing the device stability. This tailored device has exhibited a forming-free volatile threshold switching nature (with 1 pA OFF-state current) and excellent selectivity of 10
4 with tuned uniformity and endurance characteristics. Moreover, Ag/CeO
2/SiO
2/Pt has shown outstanding direct current for 10
3 I–V cycles with low density at switching voltages. Because of such results, the implementation of CeO
2-based threshold RRAMs as the best selectors is proposed when crossbar memories are adopted [
79].
5. Electrode-Based CeO2 Memory Devices
5.1. Symmetric Electrode-Based CeO2 Memristors
Memristors containing both electrodes (the same in nature) are regarded as symmetric electrode-based memristors. In this respect, being symmetric electrode-based, spin-coated Pt/CeO2-x/Pt with a polycrystalline phase and mixed with fluorite cubic structures having 40-nm thickness of Pt layer are deposited through DC magnetron sputtering. Two fundamental damages occur in the CeO2-x film of Pt/CeO2-x/Pt cell during electroforming phenomena. Surface defects are generated in Pt/CeO2-x at the TE contact, which provides the source to create positive charge carriers into CeO2-x film. During the set process, electron tunneling is accompanied by OV ionization in Pt/CeO2-x at the TE junction. The various trapping states occurring at the metal–semiconductor junction during metal electrode fabrication is evaluated in the form of surface damage. The repeated potential field owing to the crystal is disturbed at the surface, resulting in extra energy levels. Every surface atom is ascribed to a single surface energy level existing in disallowed states.
5.2. Asymmetric Electrode-Based CeO2 Memristors
Asymmetric electrode-based memristors contain different TE and BE and show comparatively superior characteristics than symmetric electrode-based devices. The Ag/CeO
2/Pt device is prepared by providing a high-vacuum environment during magnetron sputtering and a coating structure exhibiting asymmetric electrode behavior. Ceria layers having a thickness of 27 nm are decorated over a Pt/Ti/SiO
2/Si substrate by RF magnetron sputtering. Then, a silver TE with a diameter of 200 μm is deposited on the as-prepared film with a shadow mask. The ceria thin film exhibits good compactness, which is confirmed by its average roughness of 0.38 nm. This ceria film shows sufficient crystallinity and pure phase [
32]. Meanwhile, an asymmetric Ag/CeO
2/Pt device is favored according to Wang et al. Ag filaments incorporated into the ceria conducting layer are vertically stacked in the order of BE to TE [
82], which significantly favors Ag
+ ions with high mobility compared to electrons because the ceria lattice provides a fast diffusion channel for Ag
+ ions [
32].
In the Ag/CeO2/Pt memristive structure, the variation in the corresponding rate and voltage range of the device gradually changes the resistance. It is controllable through the creation and rupture of silver filaments; the conduction phenomena corresponding to each state are also investigated.
To add, a layer 10-nm-thick CeO
2 film is decorated over the Pt BE of the Pt/Ti/SiO
2/Si substrate, which is synthesized by RF magnetron sputtering. Further, a 5-nm-thick ZnO thin film is used as a second dielectric layer that is decorated over CeO
2/Pt/Ti/SiO
2/Si with the same parameters following the CeO
2 layer deposition. The final structure is the double-layered structure of the M/ZnO/CeO
2/Pt device, for which alternative electrodes such as Ti, TaN, and TiN are deposited at normal temperature. Here, magnetron sputtering is adopted with a metal shadow mask to be circular as TEs (100-nm thick) and with a diameter of 150 μm.
6. Single-Layer and Bilayer CeO2 with Capping Layer
Most previous studies have reported that the RS behavior of CeO
2 ultrathin films often requires a forming voltage [
17]. On the contrary, a study has reported that Ce-silicate can also be structured at the CeO
x/Si junction [
85]. In this way, creating Ce-silicate may increase the density of O
Vs at the contact area [
86]. Hence, Si (buffer layer) plays a role at the contact point and in the appearance of O
Vs, thereby facilitating the modulation of the forming process, possibly by CeO
2 for achieving reversible RS. Additionally, the probability of the suppressed forming process is expected to be assured through interface engineering. However, inserting a Si buffer layer at the bottom contact would form an RRAM cell having the W/CeO
2/Si/TiN structure with a small forming voltage and CC, offering a reasonable window and endurance features compared to those devices (without Si). It is expected to improve the development of Ce-silicate with the appearance of O
Vs at the interfaces caused by the dynamic production of conducting channels toward the forming process.
Moreover, the behavior of W/CeO
2/Si/TiN is easily improvable by optimizing the thickness of the Si buffer layer. Furthermore, following the symmetric conducting channel model, it may describe the consecutive mechanism of rupturing channels depending upon the reset voltage. Hence, the abovementioned results may provide a suitable path for voltage control to optimize device performance and deep insight into the slow and steady reset process [
87].
MnO/CeO2 heterostructures were prepared on Pt BE (150-nm thick) by RF magnetron sputtering at CeO2 and MnO targets in an Ar atmosphere at normal temperature. In addition, the MnO layer top area was decorated with an ~100-μm-diameter Ag TE by thermal evaporation with a shadow mask. Further, the Ag/MnO/CeO2/Pt cells were evaluated in terms of the stability in BRS characteristics, showing a high resistance ratio during the forming-free mechanism. In this way, the device always remains in HRS.
The oxygen annealing effect attributed to the RS properties of bilayer TiN/ZnO/CeO2-x/Pt structures was analyzed. The switching trend for annealing and un-annealing effects on these devices revealed that with a small increment in the forming voltage, there may be a SET/RESET voltage drop. In the study, the endurance performance was critically improved in annealed oxygen ambient at an optimal temperature of 400 °C (with reduced OVs) in the ZnO/CeO2-x film.
7. Doped CeO2-Based Memristors
The RS improvement trends in CeO2-based memristors have been analyzed through charge dynamics by using Al as the dopant. Here, results have indicated that Ti/CeO2: Al/Pt device sandwiching, always offers promising and attractive switching characteristics. An Al-doped device in the negative-forming mode is depicted by the left inset, while the right inset shows the variation in endurance. Further, the minimum forming voltage modulated the stability in SET/RESET voltages. In addition, an improved endurance (>104) of switching cycles having window of ROFF/RON > 102 was observed compared to the undoped Ti/CeOx/Pt structure.
The photochemical metal–organic deposition procedure is utilized as it is comparatively stable against humidity and temperature owing to the beneficial photochemical metallic–organic precursor (main material), whereas chemical process is primarily initiated under UV irradiation. XRD as well as Raman spectrum results have increasingly revealed the occurrence of lattice shrinkage which induces and increases the structural alteration caused by O
V formation with the Y dopant. Ce
1-xY
xO
2-y devices have exhibited bipolar filamentary behavior of RS and consequently both resistance states due to the decline in forming voltage with an increment in Y doping-induced rise in O
V density. However, the ON/OFF ratio decreases with an increment in Y density owing to reducing HRSs. Moreover, when the recovery of injecting oxide area associated with HRS switching is rendered, it causes defect sites comprising bounded electrons generated by yttrium. Spectro-microscopy revealed that ceria loses 24% oxygen during LRS, displaying a resistance variation of five orders of magnitude [
97]. Three elements (Ca, Zr, and Gd) have been utilized as dopants in CeO
2 film sandwiching into Pt/CeO
2/Pt devices. In this case, the switching characteristic has been found to be unipolar. The electrical measurement examination for Gd and Zr dopants in the Pt/CeO
2/Pt structure exhibited a resistance ratio of 104, improved retention stability with 104 s at 25 °C, and endurance of 1500 sweeping cycles.
By contrast, a Ca-doped device demonstrated the opposite trends. However, all results showed that chemical defects with O
V concentration in metallic Gd and Zr have a decisive impact compared to Ca doping in CeO
2 films. Further, XPS analysis indicated vital oxygen-containing film activation in forming conducting channels, leading to resistance alteration within the conducting layer [
98]. Further, the chemical-bonding energy obtained by XPS analysis revealed comparable undoped components; the Gd/Zr-doped cells possessed lower CeO
2-bonding energy, leading to stability in configuration conversion. On the contrary, the Ca-doped components showed higher CeO
2-bonding energy, leading to unstable configuration conversion. In conclusion, the said dopants in ultrathin films afforded resistance stability, and TEM results indicated that Zr dopant was much better than Gd dopant for the RS behavior of the CeO
2-based RRAM devices.
8. Neuromorphic Applications
8.1. Single-Layer and Bilayer CeO2-Based Synaptic Devices
Metal oxide-based memristors possess the potential for the advancement of scalable and highly efficient brain-inspired computing systems. Among these systems, oxide-based memristors display inherent electronic analog switching similar to biological synapses. For example, CeO2-based bilayer memristors occupying forming-free, low-voltage potential, and high energy efficiency and reliability play a vital role in biological synapses. Because of pulse measurement, analog behavior may be directly programmed in intermediate resistance states in such devices. Therefore, STDP may be implemented, strictly following spike-dependent Hebbian artificial learning.
8.2. Spike-Timing-Based Learning System
Moreover, CeO2 with an HfOx capping layer exhibits spike-based-learning operations that have shown novel behavior in terms of high efficiency and compactness for managing unstructured information. In these systems, the learning process is necessarily followed by spike-based Hebbian learning, proving that it is STDP, as it clearly describes the synapse strength variation during a time interval corresponding to presynaptic and postsynaptic neuron spiking. To perform these activities, a mean spiking rate of 1 MHz (105 times) is evaluated in the human brain. Moreover, the period is considered as 1 s to refresh the neurons’ existing position while calculating synaptic currents, whereas neuron-spiking probability is taken as 0.01 in the central nervous system.
8.3. Potentiation and Depression Behaviors
A symmetric electrode, such as a Pt/CeO
2/Pt device, has demonstrated synaptic-dependent potentiation and depression behaviors showing polarity-oriented analog switching. Here, the synaptic weight variation is controlled by parameters such as amplitude, width, and pulses, resulting in an artificial synaptic device for neuromorphic computing systems [
18].
8.4. Potentiation Motion and Synaptic Weight Decay
A study [
20] illustrates the consecutive increment in current at +2 and +6 V during repeated pulses and width of 50 ms with 30 repetitions in potentiation dynamics, and
the study shows normalized memory retention when potentiation is slowly reduced during time
t. Therefore, synaptic weight decay is equivalent to the human memory–forgetting curve, the STP, whereas the gradual decay of final synaptic weight denotes LTP [
102]. On the contrary, biotic synapses manage the input information and correspondingly rearrange the memory states toward a synapse.
Further, quantitative analysis has revealed the distinguished rehearsal effect to enhance memory retention. The gradual decrement in retention with time and the decaying rate significantly decreases with increasing number of stimulation (N). Herein, the rehearsal mechanism with repeating pulses (N = 70) may significantly enhance the synaptic weight variation as 75–618 nA, while the relaxation time is 24–580 s, and is firmly following the tendency reported by Chang et al. [
102], as the resistance variation due to O
V diffusion is improved and stabilized under repeated stimulation.
8.5. Short- and Long-Term Plasticity
Analog synaptic weight modulation has been proved to show linearity and symmetric behavior. Therefore, it demonstrates LTS through resistance variation in a Pt/ITO/CeO2/Pt memristor rather than Pt/CeO2/Pt memristive memory, possessing nonlinearity and asymmetric resistance variations. The same resistive memristor displays linearity and symmetric resistance variation trends associated with various voltages with opposite polarities toward synaptic potentiation and depression functions. Additionally, the memristor also exhibits considerable LTS concerning controllable synapse weight with time, which may be extracted from the capping layer (ITO). It behaves like a source of OIs in the CeO2 layer for retaining resistance variation.
By contrast, classic nonvolatile memory may disclose long-term retention of memory levels. Additionally, the current decline over time in the potentiation process for the Pt/CeO2/Pt device and Pt/ITO/CeO2/Pt memristor is considered comparable. The current decay comparison with identical ranges and pulses of various amplitudes is performed in these memristors. Primarily, the reference memristor demonstrates voltage pulses as +6–+9 V with a corresponding width of 50 ms applied for 10 cycles, and subsequently, the read current generated by +2 V during 10 cycles in 10 s. Further, to analyze the current decay during 100 s, all steps are repeated again 10 times. The above procedure repeats itself in memristor functioning by utilizing a pulse amplitude of +8–+11 V.
8.6. Pavlov’s Dog Experiment-Based Synoptic Study
More recently, an artificial neural network has been considered the hottest research spot for advanced science and technology. The CeO
2 exhibits excellent performance among various oxide-based materials, such as longer retention with healthier stability. However, its use in artificial neural synapses is still questionable. In this regard, a Ag/CeO
2/Pt memristive-type device has been realized toward the selected target. Herein, the artificial synaptic functions are successfully explored, and a sequential neuromorphic system simulation has been updated. In addition, the relations among the pulse arrangement parameters involving resistance states owing to synapse devices have also been investigated.
8.7. Latest Development in Ceria-Based Neuromorphic Computing
These potentiation and depression behaviors arise owing to the incorporation of a lower concentration of OVs within the Gd-doped ceria (GDC) layer when combined with CeO2. This leads to oxygen vacancy redistribution and unique synaptic weight redistribution behaviors. The distinct trends in synaptic weight update for polarity-dependent potentiation and depression voltages are attributed to the stacking order of CeO2 and GDC.
For biological synapses, one of the most crucial neuromorphic characteristics is STDP. STDP demonstrates that when the pre-spike signal precedes the post-spike signal (Δt > 0), it leads to long-term potentiation (LTP), resulting in an increase in synaptic weight (w). Conversely, if the post-spike follows the pre-spike (Δt < 0), long-term depression (LTD) occurs, leading to a decrease in synaptic weight (w).
9. Conclusions
High-k oxide-based materials are extensively suggested as promising memristors; however, they are still challenging in neuromorphic studies. CeO2 has become more efficient and advanced in RRAM technology, as it covers the maximum gap left behind in the memory field. Therefore, CeO2-based memristors have been widely used because they show substantial behaviors in the filamentary mechanism and classification, optimum switching behaviors (unipolar, bipolar, and threshold) depending upon the nature of electrodes (symmetric and asymmetric), and switching layers (single with capping layer, and doped-insulating layer).
This entry is adapted from the peer-reviewed paper 10.3390/nano13172443
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