Encyclopedia
Gallium氮化鎵 nitride (GaN) is a wide-bandgap semiconductor material with excellent electrical and optical properties, making it a promising candidate for various electronic and optoelectronic devices. In particular, the unique characteristics of GaN make it a popular choice for high-power and high-frequency applications, such as power electronics, RF amplifiers, and light-emitting diodes (LEDs).是一種寬帶隙半導體材料，具有優異的電學和光學特性，使其成為各種電子和光電器件的有前途的候選者。特別是，GaN 的獨特特性使其成為高功率和高頻應用的熱門選擇，例如電力電子、RF 放大器和發光二極管 (LED)。
- gallium nitride
- high electron mobility transistor
- GaN on Si/SiC/QST
1. Introduction
一、簡介
Gallium Nitride (GaN) is a wide-bandgap semiconductor material with excellent electrical and optical properties, making it a promising candidate for various electronic and optoelectronic devices. In particular, the unique characteristics of GaN make it a popular choice for high-power and high-frequency applications, such as power electronics, RF amplifiers, and light-emitting diodes (LEDs). One of the key challenges to realizing the full potential of GaN devices is the quality of the epitaxial layer. The epitaxial layer is a thin layer of GaN grown on a substrate, and it plays a crucial role in determining the performance and reliability of GaN devices. Therefore, a thorough understanding of the epitaxial growth process and the structural characteristics of the epitaxial layer is necessary.
In recent years, significant progress has been made in improving the quality of GaN epitaxial layers by developing advanced growth techniques and optimizing process parameters. The issues in GaN epitaxial layers are attributed to various factors, including defects, traps, and dislocations in the material. These defects serve as sites for electron capture and recombination, leading to local heating and thermal runaway. In addition, the high electric fields in GaN devices lead to collision ionization and the generation of electron-hole pairs, further exacerbating the breakdown problem. To address the breakdown problem in GaN devices, scientists have developed various solutions. One approach is to optimize the growth conditions of the GaN epitaxial layer to reduce the density of defects and dislocations. This is achieved through the use of advanced growth techniques (such as MOCVD and molecular beam epitaxy (MBE)) and the combination of buffer layers and strain engineering. Another approach is to develop new device structures and architectures that can mitigate the issue of defects. For example, the use of field plates, edge termination structures, and deep trench isolation helps to reduce the electric field concentration and improve the breakdown voltage of GaN devices. Additionally, the use of advanced gate dielectrics, such as Al2O3 and HfO2, helps to reduce gate leakage and improve the reliability of the devices.
2. GaN Epitaxy
GaN epitaxy是一種寬帶隙半導體材料，具有出色的電學和光學特性 on Si (111)[ 1,2,3 substrate] ，使其成為各種電子和光電子器件的有前途的候選材料。特別是，GaN 的獨特特性使其成為高功率和高頻應用的熱門選擇 faces[ issues related4、5、6、7 ] to，例如電力電子[ lattice8、9 mismatch] 、 betweenRF the substrate放大器 [ and6、7 the]、和發光二極管 epitaxial layer.(LED) [ This10 mismatch, leads11 to, high-density12 threading dislocations and other defects, which impact the performance of the final device13]. To實現 mitigate this problem, various techniques have beenGaN 器件全部潛力的關鍵挑戰之一是外延層的質量。外延層是在襯底上生長的 GaN 薄層，它在決定 GaN 器件的性能和可靠性方面起著關鍵作用[ developed,14、15、16、17、18、19 such]。因此，必須徹底了解外延生長過程和外延層的結構特性[ as20、21、22、23、24、25 str]。2. GaN外延
Siques, such( 111 )上的GasN外延面臨與襯底和外延層之間的晶格失配相關的問題[ the99、100、101、102、103、104、105、106、107、108、109]. use of thermal 這種不匹配會導致高密度的螺紋位錯和其他缺陷，從而影響最終器件的性能。為了緩解這個問題，已經開發了各種技術，例如應變工程、缺陷減少和分級緩衝層的使用，以減少位錯的數量並提高外延層的質量。此外，Sinterface materials and optimized structural design, are necessary. The 襯底上 GaN 的熱管理是外延生長過程中需要考慮的另一個關鍵因素。Si 的高導熱性會對 GaN 外延層造成顯著的熱應力，從而導致開裂和其他缺陷。因此，適當的熱管理技術，如使用熱界面材料、優化結構設計、 Qromis substrate襯底技術 technology (QST) is designed specifically for epitaxial growth, and its thermal expansion coefficient 襯底結構專為外延生長而設計，其熱膨脹係數 (CTE) closely matches that of the epitaxial layer grown on top of it. The substrate is composed of several layers, including a polycrystalline ceramic core that provides structural support, a first adhesive layer coupled to the core, a conductive layer coupled to the first adhesive layer, a second adhesive layer coupled to the conductive layer, and a barrier layer coupled to the second adhesive layer. In addition與其上生長的外延層密切匹配。襯底由幾層組成，包括提供結構支撐的多晶陶瓷芯、耦合到芯的第一粘附層、耦合到第一粘附層的導電層、耦合到導電層的第二粘附層，以及阻擋層耦合到第二粘附層的層。除了這些層之外，襯底還包括耦合到支撐結構的氧化矽層，然後是基本上單晶的矽層。最後，外延 III-V 層耦合到單晶矽層。全面的，110 to]。這方面的一個例子是在 QST 襯底 [ 100、111、112 these]上生長更厚的緩衝層，這需要引入拉伸應力以限制原位曲率的增加。 為了克服 layers, the substrate also Sincludes an oxide silicon layer coupled to the support structure, followed by a essentially single crystal silicon layer. Finally, the epitaxial III-V layer is coupled to the single crystal silicon layer. A comprehensive review can be found in. One example in this regard is growing thicker buffer layers on 和 (Al)GaN 之間的 CTE 不匹配所帶來的挑戰，這會影響緩衝層外延生長期間晶片的機械強度，採取了額外的措施。高質量 (Al)GaN 緩衝器可以在 Si 襯底上生長，但 CTE 不匹配限制了緩衝器的質量、厚度和襯底尺寸。嘗試過的一種方法是使用非標準厚度的襯底，例如我們的 GaN-on-Si 技術中的 1150 µm，用於在 200 mm Si 襯底上生長 GaN。但是，這不是一個可擴展的解決方案。一個更實用的解決方案是使用市售的 SEMI 標準厚度工程基板，例如 QST substrates,®，它具有與 which requires introducing tensi(Ale stress to limit the increase in in-situ curvature. To)GaN 緩衝層匹配的 CTE 多晶鋁芯和良好的導熱性。這些基板展示了非凡的特性，包括高晶體質量、豐富的緩衝層厚度（>15 overcoμme the challenges brought about by the CTE mismatch between Si and）、高導熱性和大直徑（12 英寸）的可擴展性潛力。通過使用此類襯底，克服了緩衝層外延生長過程中 CTE 不匹配和機械強度問題所帶來的限制，從而能夠在具有改進的機械和熱性能的 Si 襯底上生長高質量 (Al)GaN, which 。總之，QST襯底是高質量、高性能的襯底，用於生長各種材料的外延薄膜，包括氮化物、磷化物、砷化物和其他半導體材料。 此外，GaffectsN the mechanical strength of the chip during buffer layer epitaxial growth, additional measures have been taken. High-quality (Al)GaN buffers can be grown on Si substrates,外延層和 Si 襯底之間的界面也會影響器件的性能。界面特性，例如界面粗糙度、氧化層厚度和缺陷密度，會對器件的電學和光學特性產生重大影響。因此，界面特性的優化對於在 Si 器件上實現高性能 GaN 至關重要。總之，GaN 在 Si 上的外延生長面臨著與緩衝層設計、缺陷、熱管理和界面特性相關的各種挑戰。解決這些挑戰需要仔細考慮多種因素並實施適當的技術，以確保具有可靠性能的高質量設備。 在外延工藝之後，外延層的質量通過 butPL、XRD、AFM the CTE mismatch limits the quality, thickness, and substrate size of the buffer. One method that has been attempted is using non-standard和表面掃描 (surfscan) 的測量進行評估。從這些測量中獲得的信息用於優化外延結構並改進 thicknessMOCVD substrates,配方以用於後續外延運行[ 117、118、119、120 such] as the 1150 µm used in the 。如果在晶圓上發現任何表面缺陷裂紋，則進行進一步的調查以查明原因並提高外延層的質量。 為了改善GaN-on-接觸Si technology, for growing GaN襯底導致回熔刻蝕的問題，可以採用GaN或AlN成核層作為界面層。然而，由於生長過程的限制，在實踐中只能選擇AlN成核層（NL）。表面形態和意外氧雜質的存在決定了AlN onNL 200/ Si的垂直洩漏[ mm Si substrates121、122、123、124、125、126]. However, this is not a sca有趣的是，Alable solution. A more practical solution is to use commercially available SEMI standardN NL 影響後續外延層的生長及其垂直擊穿電壓。此外，發現在具有更好表面特性的AlN NL上生長的AlGaN中間層和多對AlGaN/AlN應變層超晶格提高了垂直擊穿電壓。在應用 AlN 成核層之前，可以採用表面處理（例如噴塗一些鋁或 NH thickness3 ）來創建粗糙的 SiN x表面。這有助於減輕 engineering substrates, such as QST®, which have a polycrystallinei 襯底和 GaN 晶格之間的晶格失配引起的應力，否則會導致外延層出現裂紋和彎曲。 為了進一步緩解這個問題，使用了鋁濃度遞減的漸變緩衝層，並且通常使用 aAluminum corex with Ga CTE1−x thatN matches that of the (Al)GaN buffer and的階梯梯度層而不是線性梯度層。此外，可以插入超晶格或間斷的 AlN 層，以提高外延層的晶體質量。由於其高絕緣體特性，碳-GaN 層對於器件的性能也至關重要，因為它決定了擊穿電壓和洩漏 [ good127 thermal]。因此，實現碳摻雜的均勻性至關重要。碳摻雜有多種選擇，包括 conductivity.CH These4、C substrates2 exhibitH exceptional4、C properties,3 includingH high crystal quality8, thick和 buffeCBr lay4。一些文獻還建議使用Fers摻雜，可以提高外延層的導電性。 2020 (>15年，IMEC µm), high thermal conductivity, and the potential for scalability up計劃利用 200 mm 8 英寸 QST 襯底技術在矽上生長 GaN [ to128 12 inches in diameter. By using such substrates, the129 CTE]，這對電子行業來說是一個有前途的發展。與傳統襯底相比，該技術具有多項優勢，包括減少寄生效應、匹配襯底的 mismatch and mechanical strength issues during buffer lAlN 熱膨脹係數、高導熱性、高機械產量以及生長厚 GaN 緩衝層的能力。這些優點使實現 650 V 的高擊穿電壓成為可能，這對於大功率設備來說是必不可少的。 在GayerN外延生長領域，保證表面質量至關重要，因為它影響後續工藝和元件的最終特性。因此，表面檢測是保證外延層質量的關鍵。OM epitaxial growth have been通常用於檢查襯底和外延層的表面是否有可見的裂紋和粗糙度。AFM 是一種高分辨率技術，用於檢測納米級的表面粗糙度和形態。PL 是一種非破壞性技術，用於通過測量其光學特性來評估外延層的質量。XRD 是一種強大的技術，可以提供有關晶體質量、厚度和外延層應變的信息。 除了這些技術之外，TEM overcome.還可用於在原子水平上研究外延層中的結構缺陷。它可以提供有關晶體結構、缺陷和位錯的詳細信息，這些信息對於確定外延層的質量至關重要。After epitaxial growth, the quality of the epitaxial layer is evaluated by measurements such as PL, XRD, AFM, and surface scanning (surfscan). Information obtained from these measurements is used to optimize the epitaxial structure and improve the MOCVD recipe for subsequent epitaxial runs. If any surface defects or cracks are found on the wafer, further investigation is carried out to identify the cause and improve the quality of the epitaxial layer.
To improve the issue of melting erosion caused by GaN contacting Si substrates, GaN or AlN nucleation layers can be used as interface layers. However, due to growth process limitations, in practice, only AlN nucleation layers (NL) can be selected. The surface morphology and unexpected oxygen impurities determine the vertical leakage of AlN NL/Si. Interestingly, AlN NL affects the subsequent growth of the epitaxial layer and its vertical breakdown voltage. Furthermore, it has been found that growing AlGaN intermediate layers and multi-pairs of AlGaN/AlN strain layer superlattices on AlN NL with better surface characteristics increases the vertical breakdown voltage. Before using the AlN nucleation layer, surface treatment, such as spraying aluminum or NH3, can be used to create a rough SiNx surface. This helps to mitigate the stress caused by lattice mismatch between the Si substrate and GaN lattice, which can otherwise cause cracks and warping in the epitaxial layer.
To further alleviate this problem, a gradient buffer layer with decreasing aluminum concentration is used, and a stair-step gradient layer of AlxGa1-xN is typically used instead of a linear gradient layer. In addition, superlattices or interrupted AlN layers can be inserted to improve the crystal quality of the epitaxial layer. The carbon-GaN layer is also critical for device performance due to its high insulating properties, as it determines breakdown voltage and leakage. Therefore, achieving uniform carbon doping is crucial. There are several options for carbon doping, including CH4, C2H4, C3H8, and CBr4. Some literature also suggests using Fe doping, which can improve the conductivity of the epitaxial layer.
In 2020, IMEC planned to grow GaN on silicon using 200 mm 8-inch QST substrate technology, which is a promising development for the electronics industry. Compared to traditional substrates, this technology has many advantages, including reduced parasitic effects, a matching substrate AlN thermal expansion coefficient, high thermal conductivity, high mechanical yield, and the ability to grow thick GaN buffer layers. These advantages make it possible to achieve a high breakdown voltage of 650 V, which is essential for high-power devices.
In the field of GaN epitaxial growth, ensuring surface quality is crucial because it affects the final properties of the subsequent processes and devices. Therefore, surface inspection is critical for ensuring the quality of the epitaxial layer. OM is typically used to check if there are visible defects on the substrate and epitaxial layer surface, while SEM and TEM are used for more detailed analysis. XPS and SIMS can also be used to analyze impurities on the surface of the epitaxial layer.
