Revisiting the High-Performance Reconfigurable Computing: Comparison
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Please note this is a comparison between Version 2 by Camila Xu and Version 1 by Ali Kashif Bashir.

Modern datacenters are reinforcing the computational power and energy efficiency by assimilating field programmable gate arrays (FPGAs). The sustainability of this large-scale integration depends on enabling multi-tenant FPGAs. This requisite amplifies the importance of communication architecture and virtualization method with the required features in order to meet the high-end objective.

  • FPGA virtualization
  • datacenters
  • network on chip

1. Introduction

Today, datacenters are equipped with the heterogeneous computing resources that range from Central Processing Units (CPUs), Graphical Processing Units (GPUs), Networks on Chip (NoCs) to Field Programmable Gate Arrays (FPGAs), each suited for a certain type of operation, as concluded by Escobar et al. in [1]. They all purvey the scalability and parallelism; hence, unfold new fronts for the existing body of knowledge in algorithmic optimization, computer architecture, micro-architecture, and platform-based design methods [2]. FPGAs are considered as a competitive computational resource for two reasons, added performance and lower power consumption. The cost of electrical power in datacenters is far-reaching, as it contributes roughly half of lifetime cost, as concluded in [3]. This factor alone motivates the companies to deploy FPGAs in datacenters, hence urging the scientific community to exploit High-Performance Reconfigurable Computing (HRC).
Industrial and academic works both incorporated the FPGAs to accelerate large-scale datacenter services; Microsoft’s Catapult is one such example [4]. Putnam et al. chose FPGA over GPU on the question of power demand. The flagship project accelerated Bing search engine by 95% as compared to a software-only solution, at the cost of 10% additional power.
The deployment of FPGAs in datacenters will neither be sustainable nor economical, without realizing the multi-tenancy feature of virtualization across multiple FPGAs. To achieve this ambitious goal, the scientific community needs to master two crafts, an interconnect solution preferably Network on Chip (NoC) as a communication architecture and an improved virtualization method with all the features of an operating system. Accumulating the state of the art in a survey can foster the development in this area and direct the researchers into more focused and challenging problems. Despite of the two excellent surveys, [5] in 2004 and [6] in 2018, former one categorized the FPGA virtualization as temporal partitioning, virtualized execution, and virtual machines, while, after fourteen years, the later one classified based on abstraction levels to accommodate the future changes, but the communication architecture or interconnect possibilities are not fully explored. To address this gap, an improved survey on FPGA virtualization is presented with the coverage of network-on-chip evaluation choices as a mean to explore the communication architecture, and commentary on nomenclature of existing body of knowledge. WThe researchers revisited the network-on-chip evaluation platforms in order to highlight its importance as compared to bus-based architectures. We stretched our reviewThe researchers stretched from acceleration of standalone FPGA to FPGAs connected as a computational resource in heterogeneous environment. WeThe researchers attempted to create a synergy through combining three domains to assist the designers to choose right communication architecture for the right virtualization technique and, finally, share the work in the right language, only then, multi-tenant FPGAs in datacenters can be realized.

2. Revisiting the Nomenclature

The applications of FPGAs as computing resource are diverse that includes data analytics, financial computing and cloud computing. This broad range of applications in different areas requires efficient applications and resource management. This lays the foundation for the need of virtualizing the FPGA as a potential resource. Nomenclature is much varying due to the different backgrounds of the researchers contributing to this area. There are many such examples in literature where similar concepts or architecture is described using a different name or term. There is also an abundance of jargon terms and acronyms, which confuse the researchers rather enhancing their understanding. Table 1 identifies and lists non-standard terms in literature from the last decade.
Table 1.
Non-Standard Nomenclature Present in Literature.
Year Non-Standard Term(s) in Published Literature
2010 RAMPSoC in [7]
2011 Lightweight IP (LwIP) in [8]
2012 ASIF (Application Specific FPGA) in [9]
2013 sAES (FPGA based data protection system) in [10]
2014 PFC (FPGA cloud for privacy preserving computation in [11]
2015 CPU-Cache-FPGA in [12]
2016 HwAcc (Hardware accelerators), RIPaaS and RRaaS in [13]
2017 FPGA as a Service (FaaS) and Secure FaaS in [14]
2018 ACCLOUD (Accelerated CLOUD) in [15], FPGAVirt in [16]
2019 vFPGA-based CCMs (Custom Computing Machines) in [17]
This area is stagnated for a lack of a standard nomenclature. WThe recsearchers recommend that the scientific community should use a unified nomenclature to present the viewpoint in order to improve the clarity and precision of communication for advancing the knowledge base. WeThe researchers also recommend that this area must be referred as High-Performance Reconfigurable Computing (HRC) in literature. Moreover, it has been observed that the use of computer science language is more conveying as virtualization in FPGAs is comparable to an operating system in CPUs.

3. Revisiting the Network on Chip Evaluation Tools

Data transfers in most of the high-performance architectures are limited by memory hierarchy and communication architecture, as summarized in [19,20][18][19]. Exploiting communication architecture suggests the use of NoC, an effective replacement for buses or dedicated links in a system with large number of processing cores [21,22][20][21]. NoC is composed of several tunable parameters like network architecture, algorithm, network topology and flow control. No System on Chip (SoC) is outright without NoC, today, due to promised high communication bandwidth with low latency as compared to the alternate communication architectures. Researchers heavily rely on automated evaluation tools, where performance and power evaluation can be viewed early in design, given the complexity of NoC. Figure 1 describes a typical cycle of NoC evaluation, with FPGA being connected to a Central Processing Unit (CPU). Traffic scenarios are generated through traffic generator, sent to NoC that resides in FPGA, and the evaluation results are received through traffic receptors. Tools for FPGA based NoC prototyping are diverse architecture-wise. De Lima et al. in [23][22] identified an architectural model comprising of three layers: network, traffic, and management.
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Figure 1. Generic Architecture of Networks on Chip (NoC) Evaluation on Field Programmable Gate Arrays (FPGA)(s).
Generic Architecture of Networks on Chip (NoC) Evaluation on Field Programmable Gate Arrays (FPGA)(s).
There are four different types of network: Direct Mapping on Single or Multi FPGA(s), Fast Prototyping and Virtualization. The choice of the network affects the accuracy and resource utilization. Traffic on network can be generated in two different ways: synthetic and application-specific. Synthetic traffic is a kind of load testing to evaluate the overall performance, but it fails to forecast the performance under real traffic flow. Application-specific traffic, on the other hand, is based on the behavior of real traffic flow that is difficult to acquire but gives more accurate results. These patterns can be acquired either through trace, statistical method or executing application cores. As traces comprises of millions of packets so the size becomes a limiting factor. Running application cores to generate traffic is also resource-expensive method. Table 2 lists some FPGA based NoC evaluation tools, describing every architecture with network type, traffic type, number of routers, target board, and execution frequency, while hiding the complexity of NoC designs. The number of routers in NoC depends on the network type, architecture with relatively more routers, are based on second group type of network, fast prototyping and virtualization. WThe researchers have used the direct mapping network type in ourthe previous works due to relatively high execution frequency [24,25][23][24].
Table 2.
NoC Evaluation Tools based on FPGA(s)
.
Year Network Type Traffic Type No. of Routers Target FPGA Freq. (M.Hz.) Work
2010 Multiple FPGA Real: App. Cores 16 Virtex 5 × 5 - [26][25]
2010 Direct Mapping Real: Traces based 64 Virtex 2 45 [27][
[42][41] is suitable for the designers working on Xilinx tools. Maxeler Technologies, however, offers specific solutions, like an algorithmic contribution for memory mapping [43][42] and an area optimization technique [44][43]. Virtualization plays a relatable role to an operating system in a computer, but the term is being used in different meanings in this area, due to non-uniform nomenclature discussed earlier. Yet, the universal concept of an abstraction layer remains unchanged, a layer for the user to hide the underlying complexity of the computing machine, where the computing machine is not a traditional one, but FPGA. Many virtualization architectures have been proposed as per the requirements of the diverse applications. In 2004, a survey in this regard categorized the virtualization architectures into three broad categories, temporal partitioning, virtualized execution, and overlays [5]. Since then, no serious effort has been recorded on the classification of virtualization, until Vaishnav et al. [6] in 2018 classified the virtualization architectures based on abstraction levels. This much-needed classification contributed by Vaishnav et al. has been adopted as is, to discuss the works in this survey. WThe researchers reiterated them with some of the representative work examples in Table 3. The works have been discussed under the same abstract classification.
Table 3.
Classification of FPGA Virtualization adopted from [6].
Abstract Classification Sub-Class Work Examples References
Resource Level Overlays [45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74][44][45][46][47][48][49][50][51][52
26]
][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71] 2010 Fast Prototyping Synthetic 49 Virtex 6 50 [28][27]
[72][73]
Input Output (I/O) Virtualization [4,75,[76,77,74][78,75][79,80][4]76][77][78][79] 2011 Direct Mapping Real: Traces based 25 Virtex 5 - [29][28]
2011 Virtualization Real: Traces based 256 Virtex 6
Node Level Virtual Machine Monitors [81,82,83,84][80][81][82][83]
Shells [4,41,75,76,77,78,85,86,87,88,89,93,94,95,96,97][4][40][74][75][76][77][84][8590,][91,8692,][87][88][89][90][91][92][93][94][95][96]
Scheduling [82,152 89,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112][81][88][97][98][99][100[30][29]
][101][102][103][104][105][106][107][108][109][110][111] 2011 Fast Prototyping Synthetic 576 Virtex 6 300 [31][30]
Multi Node Level Custom Clusters [113,114,115,116,117][112][113][114][115][116] 2011 Virtualization Real: App. Cores 64 Virtex 2
Frameworks [77,103- ,118,119,120,121,122,123][76][102][117][118][119][120][121][122][32][31]
2011 Virtualization Real: App. Cores
Cloud Services [4,40,124,125,16 ]Virtex 5 3, 15 [33][32]
2011 Direct Mapping Synthetic 36 Virtex 5 - [34][33]
2012 Direct Mapping Real: App. Cores 9 Virtex 5 - [35][34]
2013 Multiple FPGA Synthetic 18 Virtex 5 × 2 - [36][35]
2014 Virtualization Synthetic 1024 Virtex 7 42 [37][36]
[4]126,[39]127,[128,129,123][ 2015 Direct Mapping Synthetic 64 Virtex 6 50 [38][37]
124][125][126][127][128]130[129] 2016 Direct Mapping Synthetic 16 Virtex 6 250 [13]
2017 Direct Mapping Synthetic 16 Virtex 6 250 [24][23]
2018 Direct Mapping Synthetic 16 Virtex 6 250 [25][24]
These evaluation platforms assist the designers to reach the design-specific communication architecture, meeting most of the requirement specifications, for a certain application. These evaluation platforms take comparatively more time to synthesize the change, while on the other hand, a simulator can accommodate the same change in much lesser time. Designers offer dynamic reconfiguration, as a peroration to this limitation, but simulators are still the first choice of many entry-level researchers. However, the choice of NoC to realize the future datacenters with multi-tenant multi-FPGAs is yet to explore. The linking of several computational nodes becomes complicated and affects the performance of the overall system. Although NoC is not the only choice for communication within an FPGA as well as among multiple FPGAs but offer a competitive and promising solution. Other solutions include traditional bus, bus combined with a soft shell, different types of soft NoC and hard NoC. Many comparative studies evaluated these choices based on parameters like useable bandwidth, area consumption, latency, wire requirement and routing congestion. The way NoC is generated, also affects the performance so designers must be careful while choosing the NoC or an alternate for their design.

4. Revisiting the FPGA Virtualization

Resources are time multiplexed in a cloud services provider datacenter, referred as Infrastructure as a Service (IaaS). The sharing of resources is achieved through virtualization, an abstraction layer for hiding the physical resources from users. The process of virtualization raises issues like ease-of-use, privacy and performance but yet IaaS provide individual users and small organizations with an economic choice of renting over spending on infrastructure. Other than an academic example, such as SAVI testbed [39][38], industry offers plenty of solutions that are equally popular among designers. Amazon Web Services EC2 [40][39], IBM Zurich [41][40], and Intel are important competitors. Alveo on the Nimbix Cloud
Although there are many features of virtualization like management, scheduling, adoptability, segregation, scalability, performance-overhead, availability, programmability, time-to-market, security, but the most important feature in the context of scope of this research is the multi-tenancy because it is essential for a sustainable and economically viable deployment in datacenters. FPGA has two types of fabric: reconfigurable and non-reconfigurable. The virtualization for the non-reconfigurable fabric is the same as of CPU, but there are several variations when it comes to the virtualization of the reconfigurable fabric.

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